LTC2960
6
2960fa
For more information www.linear.com/LTC2960
pin FuncTions
ADJ: Reset Threshold Adjustment Input. Tie to resistive
divider to configure desired reset threshold.
DV
CC
: (LTC2960-3/LTC2960-4) Logic Supply Input. Used
for setting the logic swing of the RST and OUT outputs.
Useful for interfacing with logic voltages different from
V
CC
. Bypass DV
CC
with 0.1µF to GND. Grounding DV
CC
allows OUT and RST to act as open drain outputs.
Exposed Pad (DFN Only): Exposed pad may be left floating
or connected to device ground.
GND: Device ground.
IN
–
: (LTC2960-2/LTC2960-4) IN
–
Threshold Adjustment
Input. Tie to resistive divider to configure required thresh-
old. Tie
to GND if unused.
IN
+
: (LTC2960-1/LTC2960-3) IN
+
Threshold Adjustment
Input. Tie to resistive divider to configure required thresh-
old. Tie
to GND if unused.
MR
: Manual Reset Input. Attach a push-button switch or
logic signal between this input and ground. A logic low on
this input pulls RST low. When the MR input returns to
logic high, RST returns high after a reset timeout period
has expired. Leave open if unused.
OUT: (LTC2960-1/LTC2960-3) Pulls low when monitored
voltage falls below the IN
+
threshold. Released when
the IN
+
voltage rises above its threshold by 5%. For the
LTC2960-3, OUT is driven by DV
CC
when logic high. OUT
is open drain if DV
CC
is grounded. Leave open if unused.
(LTC2960-2/LTC2960-4) OUT pulls low when the moni-
tored voltage
rises
above the IN
–
threshold. Released when
monitored voltage falls below IN
–
threshold by 5%. For the
LTC2960-4, OUT is driven to DV
CC
for a logic high. OUT
is open drain if DV
CC
is grounded. Leave open if unused.
RST: Reset Output. Pulls low when monitored voltage falls
below the reset (ADJ) threshold. RST is released after
monitored voltage exceeds the reset threshold plus 2.5%
hysteresis and after reset timeout period has expired. For
the LTC2960-3/LTC2960-4, RST is driven to DV
CC
for a
logic high. RST is open drain if DV
CC
is grounded. Leave
open if unused.
RT: (LTC2960-1/LTC2960-2) Reset Timeout Period Se
-
lection Input. Tie to GND for 15ms delay. Tie to V
CC
for
200ms delay.
V
CC
: Power Supply Input. When V
CC
falls below the falling
UVLO threshold, the outputs are pulled low. If V
CC
falls
below 1.2V the logic state of the outputs cannot be guar-
anteed. Bypass
V
CC
with 0.1µF to GND. Use appropriate
voltage rating for bypass capacitor.
