December 2010
IPUG87_01.0
Median Filter IP Core User’s Guide
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG87_01.0, December 2010 2 Median Filter IP Core User’s Guide
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Chapter 2. Functional Description ........................................................................................................ 6
Key Concepts........................................................................................................................................................ 6
Block Diagram....................................................................................................................................................... 6
Active Region Selection ........................................................................................................................................ 7
Median Arithmetic Unit .......................................................................................................................................... 7
Primary I/O ............................................................................................................................................................ 8
Interface Descriptions ........................................................................................................................................... 8
Video Input/Output ....................................................................................................................................... 8
Timing Specifications ............................................................................................................................................ 9
Chapter 3. Parameter Settings ............................................................................................................ 10
Basic Options Tab............................................................................................................................................... 10
Filter Specifications .................................................................................................................................... 11
Active Region ............................................................................................................................................. 11
Data Features ............................................................................................................................................ 12
Advanced Options Tab........................................................................................................................................ 12
Memory Type ............................................................................................................................................. 12
Optional Ports ............................................................................................................................................ 12
Synthesis Options ...................................................................................................................................... 12
Chapter 4. IP Core Generation............................................................................................................. 13
Licensing the IP Core.......................................................................................................................................... 13
Getting Started .................................................................................................................................................... 13
IPexpress-Created Files and Top Level Directory Structure............................................................................... 15
Instantiating the Core .......................................................................................................................................... 16
Running Functional Simulation ........................................................................................................................... 16
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 16
Hardware Evaluation........................................................................................................................................... 17
Enabling Hardware Evaluation in Diamond................................................................................................ 17
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 17
Updating/Regenerating the IP Core .................................................................................................................... 18
Regenerating an IP Core in Diamond ........................................................................................................ 18
Regenerating an IP Core in ispLEVER ...................................................................................................... 18
Chapter 5. Support Resources ............................................................................................................ 20
Lattice Technical Support.................................................................................................................................... 20
Online Forums............................................................................................................................................ 20
Telephone Support Hotline ........................................................................................................................ 20
E-mail Support ........................................................................................................................................... 20
Local Support ............................................................................................................................................. 20
Internet ....................................................................................................................................................... 20
References.......................................................................................................................................................... 20
LatticeECP2/M ........................................................................................................................................... 20
LatticeECP3 ............................................................................................................................................... 20
LatticeXP2.................................................................................................................................................. 20
Revision History .................................................................................................................................................. 20
Appendix A. Resource Utilization ....................................................................................................... 21
LatticeXP2 FPGAs .............................................................................................................................................. 21
Ordering Part Number................................................................................................................................ 21
Table of Contents
Lattice Semiconductor Table of Contents
IPUG87_01.0, December 2010 3 Median Filter IP Core User’s Guide
LatticeECP3 FPGAs............................................................................................................................................ 21
Ordering Part Number............................................................................................................................... 21
LatticeECP2/S FPGAs ........................................................................................................................................ 21
Ordering Part Number............................................................................................................................... 22
LatticeECP2M/S FPGAs ..................................................................................................................................... 22
Ordering Part Number................................................................................................................................ 22

MED-FILT-X2-U1

Mfr. #:
Manufacturer:
Lattice
Description:
IP CORE MEDIAN FILTER XP2 CONF
Lifecycle:
New from this manufacturer.
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