IPUG87_01.0, December 2010 13 Median Filter IP Core User’s Guide
This chapter provides information on how to generate the Median Filter IP core using the Diamond or ispLEVER
software IPexpress tool, and how to include the core in a top-level design.
Licensing the IP Core
An IP core- and device-specific license is required to enable full, unrestricted use of the Median Filter IP core in a
complete, top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at:
http://www.latticesemi.com/products/intellectualproperty/aboutip/isplevercoreonlinepurchas.cfm
Users may download and generate the Median Filter IP core and fully evaluate the core through functional simula-
tion and implementation (synthesis, map, place and route) without an IP license. The Median Filter IP core also
supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that
operate in hardware for a limited time (approximately four hours) without requiring an IP license. See “Hardware
Evaluation” on page 17 for further details. However, a license is required to enable timing simulation, to open the
design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hardware evalu-
ation timeout limitation.
Getting Started
The Median Filter IP core is available for download from the Lattice IP Server using the IPexpress tool. The IP files
are automatically installed using ispUPDATE technology in any customer-specified directory. After the IP core has
been installed, the IP core will be available in the IPexpress GUI dialog box shown in Figure 4-1.
The IPexpress tool GUI dialog box for the Median Filter IP core is shown in Figure 4-1. To generate a specific IP
core configuration the user specifies:
• Project Path – Path to the directory where the generated IP files will be located.
• File Name – “username” designation given to the generated IP core and corresponding folders and files.
• (Diamond) Module Output – Verilog or VHDL.
• (ispLEVER) Design Entry Type – Verilog HDL or VHDL.
• Device Family – Device family to which IP is to be targeted (e.g. Lattice ECP2M, LatticeECP3, etc.). Only fami-
lies that support the particular IP core are listed.
• Part Name – Specific targeted part within the selected device family.
Chapter 4:
IP Core Generation