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MED-FILT-X2-U1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Lattice Semiconductor IP Core Generation
IPUG87_01.0, December 2010 16 Median Filter IP Core User’s Guide
Table 4-2 provides a list of key additional files providing IP core generation status information and command line
generation capability are generated in the user's project directory.
Instantiating the Core
The generated Median Filter IP core package includes black-box (<username>_bb.v) and instance (<user-
name>_inst.v) templates that can be used to instantiate the core in a top-level design. An example RTL top-level
reference source file that can be used as an instantiation template for the IP core is provided in
\<project_dir>\median_eval\<username>\src\rtl\top. Users may also use this top-level reference as
the starting template for the top-level for their complete design.
Running Functional Simulation
Simulation support for the Median Filter IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator,
Mentor Graphics ModelSim simulator. The functional simulation includes a configuration-specific behavioral model
of the Median Filter IP core. The test bench sources stimulus to the core, and monitors output from the core. The
generated IP core package includes the configuration-specific behavior model (<username>_beh.v) for functional
simulation in the “Project Path” root directory. The simulation scripts supporting ModelSim evaluation simulation is
provided in \<project_dir>\median_eval\<username>\sim\modelsim\scripts. The simulation script
supporting Aldec evaluation simulation is provided in \<project_dir>\median_eval\<user-
name>\sim\aldec\scripts. Both Modelsim and Aldec simulation is supported via test bench files provided in
\<project_dir>\median_eval\testbench. Models required for simulation are provided in the corresponding
\models folder. Users may run the Aldec evaluation simulation by doing the following:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro.
3. Browse to folder \<project_dir>\median_eval\<username>\sim\aldec\scripts and execute one
of the "do" scripts shown.
Users may run the Modelsim evaluation simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose the folder
<project_dir>\median_eval\<username>\sim\modelsim\scripts.
3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown.
Note: When the simulation is complete, a pop-up window will appear asking “Are you sure you want to finish?”
Choose No to analyze the results. Chosing Yes closes ModelSim.
Synthesizing and Implementing the Core in a Top-Level Design
Synthesis support for the Median Filter IP core is provided for Mentor Graphics Precision or Synopsys Synplify. The
Median Filter IP core itself is synthesized and is provided in NGO format when the core is generated in IPexpress.
Users may synthesize the core in their own top-level design by instantiating the core in their top-level as described
previously and then synthesizing the entire design with either Synplify or Precision RTL synthesis.
Table 4-2. Additional Files
File Description
<username>_generate.tcl
This file is created when the GUI “Generate” button is pushed. This file may be run from com-
mand line.
<username>_generate.log This is the synthesis and map log file.
<username>_gen.log This is the IPexpress IP generation log file
Lattice Semiconductor IP Core Generation
IPUG87_01.0, December 2010 17 Median Filter IP Core User’s Guide
The top-level file <username>_eval_top.v provided in
\<project_dir>\median_eval\<username>\src\top
supports the ability to implement the Median Filter core in isolation. Push-button implementation of this top-level
design with either Synplify or Precision RTL Synthesis is supported via the project files
<username>_eval.ldf (Diamond) or .syn (ispLEVER) located in the
\<project_dir>\median_eval\<username>\impl\synplify
and the
\<project_dir>\median_eval\<username>\impl\precision directories, respectively.
To use this project file in Diamond:
1. Choose File > Open > Project.
2. Browse to \<project_dir>\median_eval\<username>\impl\(synplify or precision) in the Open
Project dialog box.
3. Select and open <username>.ldf. At this point, all of the files needed to support top-level synthesis and imple-
mentation will be imported to the project.
4. Select the Process tab in the left-hand GUI window.
5. Implement the complete design via the standard Diamond GUI flow.
To use this project file in ispLEVER:
1. Choose File > Open Project.
2. Browse to \<project_dir>\median_eval\<username>\impl\(synplify or precision) in the Open
Project dialog box.
3. Select and open <username>.syn. At this point, all of the files needed to support top-level synthesis and imple-
mentation will be imported to the project.
4. Select the device top-level entry in the left-hand GUI window.
5. Implement the complete design via the standard ispLEVER GUI flow.
Hardware Evaluation
The Median Filter IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create
versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without
requiring the purchase of an IP license. It may also be used to evaluate the core in hardware in user-defined
designs.
Enabling Hardware Evaluation in Diamond
Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be
enabled/disabled in the Strategy dialog box. It is enabled by default.
Enabling Hardware Evaluation in ispLEVER
In the Processes for Current Source pane, right-click the Build Database process and choose Properties from the
dropdown menu. The hardware evaluation capability may be enabled/disabled in the Properties dialog box. It is
enabled by default.
Lattice Semiconductor IP Core Generation
IPUG87_01.0, December 2010 18 Median Filter IP Core User’s Guide
Updating/Regenerating the IP Core
By regenerating an IP core with the IPexpress tool, you can modify any of its settings including device type, design
entry method, and any of the options specific to the IP core. Regenerating can be done to modify an existing IP
core or to create a new but similar one.
Regenerating an IP Core in Diamond
To regenerate an IP core in Diamond:
1. In IPexpress, click the Regenerate button.
2. In the Regenerate view of IPexpress, choose the IPX source file of the module or IP you wish to regenerate.
3. IPexpress shows the current settings for the module or IP in the Source box. Make your new settings in the Tar-
get box.
4. If you want to generate a new set of files in a new location, set the new location in the IPX Target File box. The
base of the file name will be the base of all the new file names. The IPX Target File must end with an .ipx exten-
sion.
5. Click Regenerate. The module’s dialog box opens showing the current option settings.
6. In the dialog box, choose the desired options. To get information about the options, click Help. Also, check the
About tab in IPexpress for links to technical notes and user guides. IP may come with additional information. As
the options change, the schematic diagram of the module changes to show the I/O and the device resources
the module will need.
7. To import the module into your project, if it’s not already there, select Import IPX to Diamond Project (not
available in stand-alone mode).
8. Click Generate.
9. Check the Generate Log tab to check for warnings and error messages.
10.Click Close.
The IPexpress package file (.ipx) supported by Diamond holds references to all of the elements of the generated IP
core required to support simulation, synthesis and implementation. The IP core may be included in a user's design
by importing the .ipx file to the associated Diamond project. To change the option settings of a module or IP that is
already in a design project, double-click the module’s .ipx file in the File List view. This opens IPexpress and the
module’s dialog box showing the current option settings. Then go to step 6 above.
Regenerating an IP Core in ispLEVER
To regenerate an IP core in ispLEVER:
1. In the IPexpress tool, choose Tools > Regenerate IP/Module.
2. In the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core
you wish to regenerate, and click Open.
3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core
in the Source Value box. Make your new settings in the Target Value box.
4. If you want to generate a new set of files in a new location, set the location in the LPC Target File box. The base
of the .lpc file name will be the base of all the new file names. The LPC Target File must end with an .lpc exten-
sion.
5. Click Next. The IP core’s dialog box opens showing the current option settings.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MED-FILT-X2-U1

Mfr. #:
Buy MED-FILT-X2-U1
Manufacturer:
Lattice
Description:
IP CORE MEDIAN FILTER XP2 CONF
Lifecycle:
New from this manufacturer.
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