4. Circuit Guidelines
4.1 More Information
Refer to Application Note QTAN0002, "Secrets of a Successful QTouch
®
Design", and the "Touch
Sensors Design Guide" (both downloadable from http://www.microchip.com), for more information on
construction and design methods.
4.2 Sample Capacitor
Cs is the charge sensing sample capacitor. The required Cs value depends on the thickness of the panel
and its dielectric constant. Thicker panels require larger values of Cs. Typical values are 2 nF to 50 nF
depending on the sensitivity required; larger values of Cs demand higher stability and better dielectric to
ensure reliable sensing.
The Cs capacitor should be a stable type, such as X7R ceramic or PPS film. For more consistent sensing
from unit to unit, 5% tolerance capacitors are recommended. X7R ceramic types can be obtained in 5%
tolerance at little or no extra cost. In applications where high sensitivity (long burst length) is required, the
use of PPS capacitors is recommended.
For battery powered operation, a higher value sample capacitor is recommended (typical value 8.2 nF).
4.3 UDFN/USON Package Restrictions
The central pad on the underside of the UDFN/USON chip is connected to ground. Do not run any tracks
underneath the body of the chip, only ground.
4.4 Power Supply and PCB Layout
See Section 5.2 for the power supply range. At 3V, current drain averages less than 500 μA in Fast mode.
If the power supply is shared with another electronic system, care should be taken to ensure that the
supply is free of digital spikes, sags, and surges which can adversely affect the QT1010. The QT1010 will
track slow changes in Vdd, but it can be badly affected by rapid voltage fluctuations. It is highly
recommended that a separate voltage regulator be used just for the QT1010 to isolate it from power
supply shifts caused by other components.
If desired, the supply can be regulated using a Low Dropout (LDO) regulator, although such regulators
often have poor transient line and load stability. See Application Note QTAN0002, "Secrets of a
Successful QTouch
®
Design" for further information.
Parts placement: The chip should be placed to minimize the SNSK trace length to reduce low frequency
pickup, and to reduce stray Cx, which degrades gain. The Cs and Rs resistors (see Figure 1-1) should be
placed as close to the body of the chip as possible so that the trace between Rs and the SNSK pin is very
short, thereby reducing the antenna-like ability of this trace to pick up high frequency signals and feed
them directly into the chip. A ground plane can be used under the chip and the associated discrete
components, but the trace from the Rs resistor and the electrode should not run near ground to reduce
loading.
For best EMC performance, the circuit should be made entirely with SMT components.
AT42QT1010
© 2017 Microchip Technology Inc.
Datasheet
DS40001946A-page 15
