ADuM4160 Data Sheet
Rev. D | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
BUS1
1
GND
1
*
2
V
DD1
3
PDEN
4
V
BUS2
16
GND
2
*
15
V
DD2
14
SPD
13
SPU
5
PIN
12
UD–
6
DD–
11
UD+
7
DD+
10
GND
1
*
8
GND
2
*
9
ADuM4160
TOP VIEW
(Not to Scale)
NC = NO CONNECT
*
PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND
1
IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND
2
IS RECOMMENDED.
08171-003
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Direction Description
1 V
BUS1
Power
Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect V
BUS1
to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
V
BUS1
to V
DD1
and to the external 3.3 V power supply. Bypass to GND
1
is required.
2 GND
1
Return Ground 1. Ground reference for Isolator Side 1.
3 V
DD1
Power
Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V
DDI
pin
should be used for a bypass capacitor to GND
1
. Signal lines that may require pull up, such as PDEN and
SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V
BUS1
to
V
DD1
and to the external 3.3 V power supply. Bypass to GND
1
is required.
4 PDEN Input
Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to V
DD1
.
When connected to GND
1
while exiting from reset, the downstream pull-down resistors are
disconnected, allowing buffer impedance measurements.
5 SPU Input
Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied
low. This input must be set high via connection to V
DD1
or set low via connection to GND
1
and must
match Pin 13.
6 UD− I/O Upstream D−.
7 UD+ I/O Upstream D+.
8 GND
1
Return Ground 1. Ground reference for Isolator Side 1.
9 GND
2
Return Ground 2. Ground reference for Isolator Side 2.
10 DD+ I/O Downstream D+.
11 DD− I/O Downstream D−.
12 PIN
Input
Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can
be tied to V
DD2
for operation on power-up, or tied to an external control signal for applications requiring
delayed enumeration.
13 SPD Input
Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied
low. This input must be set high via connection to V
DD2
or low via connection to GND
2
, and must match
Pin 5.
14 V
DD2
Power
Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V
DD2
pin
should be used for a bypass capacitor to GND
2
. Signal lines that may require pull-up, such as SPD, can be
tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V
BUS2
to V
DD2
and to the
external 3.3 V power supply. Bypass to GND
2
is required.
15 GND
2
Return Ground 2. Ground reference for Isolator Side 2.
16 V
BUS2
Power
Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect V
BUS2
to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
V
BUS2
to V
DD2
and to the external 3.3 V power supply. Bypass to GND
2
is required.
Data Sheet ADuM4160
Rev. D | Page 9 of 16
Table 10. Truth Table, Control Signals, and Power (Positive Logic)
1
V
SPU
Input
V
BUS1
, V
DD1
State
V
UD+
,
V
UD−
State
V
SPD
Input
V
BUS2
, V
DD2
State
V
DD+
,
V
DD−
State
V
PIN
Input Notes
H Powered Active H Powered Active H
Input and output logic set for full speed logic convention
and timing.
L Powered Active L Powered Active H
Input and output logic set for low speed logic convention
and timing.
L Powered Active H Powered Active H
Not allowed: V
SPU
and V
SPD
must be set to the same value.
USB host detects communications error.
H Powered Active L Powered Active H
Not allowed: V
SPU
and V
SPD
must be set to the same value.
USB host detects communications error.
X Powered Z X Powered Z L
Upstream Side 1 presents a disconnected state to the USB
cable.
X Unpowered X X Powered Z X
When power is not present on V
DD1
, the downstream data
output drivers revert to high-Z within 32 bit times. The
downstream side initializes in high-Z state.
X Powered Z X Unpowered X X
When power is not present on V
DD2
, the upstream side
disconnects the pull-up and disables the upstream drivers
within 32 bit times.
1
H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance
output state.
ADuM4160 Data Sheet
Rev. D | Page 10 of 16
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
USB isolation in the D+/D− lines is challenging for several
reasons. First, access to the output enable signals is normally
required to control a transceiver. Some level of intelligence must
be built into the isolator to interpret the data stream and
determine when to enable and disable its upstream and down-
stream output buffers. Second, the signal must be faithfully
reconstructed on the output side of the coupler while retaining
precise timing and not passing transient states such as invalid
SE0 and SE1 states. In addition, the part must meet the low
power requirements of the suspend mode.
The iCoupler technology is based on edge detection, and,
therefore, lends itself well to the USB application. The flow of
data through the device is accomplished by monitoring the
inputs for activity and setting the direction for data transfer
based on a transition from the idle (J) state. When data
direction is established, data is transferred until either an end-
of-packet (EOP) or a sufficiently long idle state is encountered.
At this point, the coupler disables its output buffers and
monitors its inputs for the next activity
During the data transfers, the input side of the coupler holds its
output buffers disabled. The output side enables its output buffers
and disables edge detection from the input buffers. This allows
the data to flow in one direction without wrapping back through
the coupler making the iCoupler latch. Logic is included to
eliminate any artifacts due to different input thresholds of the
differential and single-ended buffers. The input state is transferred
across the isolation barrier as one of three valid states, J, K, or
SE0. The signal is reconstructed at the output side with a fixed
time delay from the input side differential input.
The iCoupler does not have a special suspend mode, nor does it
need one because its power supply current is below the suspend
current limit of 2.5 mA when the USB bus is idle.
The ADuM4160 is designed to interface with an upstream
facing low/full speed USB port by isolating the D+/D− lines.
An upstream facing port supports only one speed of operation,
thus, the speed related parameters, J/K logic levels, and D+/D−
slew rate are set to match the speed of the upstream facing
peripheral port (see
Table 1 0).
A control line on the downstream side of the ADuM4160 activates
a pull-up resistor integrated into the upstream side. This allows
the downstream port to control when the upstream port attaches
to the USB bus. The pin can be tied to the peripheral pull-up, a
control line, or the V
DD2
pin, depending on when the initial bus
connect is to be performed.
PRODUCT USAGE
The ADuM4160 is designed to be integrated into a USB
peripheral with an upstream facing USB port as shown in
Figure 4. The key design points are:
1. The USB host provides power for the upstream side of the
ADuM4160 through the cable.
2. The peripheral supply provides power to the downstream
side of the ADuM4160.
3. The DD+/DD− lines of the isolator interface with the
peripheral controller, and the UD+/UD− lines of the
isolator connect to the cable or host.
4. Peripheral devices have a fixed data rate that is set at design
time. The ADuM4160 has configuration pins, SPU and
SPD, that determine the buffer speed and logic convention
for each side. These must be set identically and match the
desired peripheral speed.
5. USB enumeration begins when either the UD+ or UD−
line is pulled high at the peripheral end of the USB cable,
which is the upstream side of the ADuM4160. Control of
the timing of this event is provided by the PIN input on the
downstream side of the coupler.
6. Pull-up and pull-down resistors are implemented inside
the coupler. Only external series resistors and bypass
capacitors are required for operation.
USB
HOST
ADuM4160
V
BUS1
V
BUS2
DD+
DD–
GND
1
DD+
3.3VV
DD2
DD–
PIN
MICRO-
CONTROLLER
POWER
SUPPLY
PERIPHERAL
08171-004
Figure 4. Typical Application
Other than the delayed application of pull-up resistors, the
ADuM4160 is transparent to USB traffic, and no modifications
to the peripheral design are required to provide isolation. The
isolator adds propagation delay to the signals comparable to a
hub and cable. Isolated peripherals must be treated as if there
were a built-in hub when determining the maximum number of
hubs in a data chain.
Hubs can be isolated like any other peripheral. Isolated hubs
can be created by placing an ADuM4160 on the upstream port
of a hub chip. This configuration can be made compliant if
counted as two hub delays. The hub chip allows the ADuM4160
to operate at full speed yet maintains compatibility with low
speed devices.

ADUM4160BRWZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Full/Low Spd USB 2.0 Digital
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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