ADUM4160BRWZ Datasheet ADUM4160BRWZ, ADUM4160BRWZ-RL, ADUM4160BRIZ-RL | P13-P15

Data Sheet ADuM4160

Rev. D | Page 11 of 16

COMPATIBILITY OF UPSTREAM APPLICATIONS

The ADuM4160 is designed specifically for isolating a USB

peripheral. However, the chip does have two USB interfaces that

meet the electrical requirements for driving USB cables. This

opens the possibility of implementing isolation in downstream

USB ports such as isolated cables, which have generic connections

to both upstream and downstream devices, as well as isolating

host ports.

In a fully compliant application, a downstream facing port must

be able to detect whether a peripheral is low speed or full speed

based on the application of the upstream pull-up. The buffers and

logic conventions must adjust to match the requested speed.

Because the ADuM4160 sets its speed by hard wiring pins, the

part cannot adjust to different peripherals on the fly.

The practical result of using the ADuM4160 in a host port is

that the port works at a single speed. This behavior is acceptable

in embedded host applications; however, this type of interface is

not fully compliant as a general-purpose USB port.

Isolated cable applications have a similar issue. The cable operates

at the preset speed only; therefore, treat cable assemblies as

custom applications, not general-purpose isolated cables.

POWER SUPPLY OPTIONS

In most USB transceivers, 3.3 V is derived from the 5 V USB bus

through an LDO regulator. The ADuM4160 includes internal

LDO regulators on both the upstream and downstream sides.

The output of the LDO is available on the V

DD1

and V

DD2

pins.

In some cases, especially on the peripheral side of the isolation,

there may not be a 5 V power supply available. The ADuM4160

has the ability to bypass the regulator and run on a 3.3 V supply

directly.

Two power pins are present on each side, V

BUSx

and V

DDx

. If 5 V

is supplied to V

BUSx

, an internal regulator creates 3.3 V to power

the xD+ and xD− drivers. V

DDx

provides external access to the

3.3 V supply to allow external bypass as well as bias for external

pull-ups. If only 3.3 V is available, it can be supplied to both

BUSx

and V

DDx

. This disables the regulator and powers the

coupler directly from the 3.3 V supply.

Figure 5 shows how to configure a typical application when the

upstream side of the coupler receives power directly from the

USB bus and the downstream side is receiving 3.3 V from the

peripheral power supply. The downstream side can run from a

5 V V

BUS2

power supply as well. It can be connected in the same

manner as V

BUS1

as shown in Figure 5, if needed.

PRINTED CIRCUIT BOARD (PCB) LAYOUT

The ADuM4160 digital isolator requires no external interface

circuitry for the logic interfaces. For full speed operation, the

D+ and D− line on each side of the device requires a 24 Ω ± 1%

series termination resistor. These resistors are not required for

low speed applications. Power supply bypassing is required at

the input and output supply pins (see Figure 5)

. Install bypass

cap

acitors between V

BUSx

and V

DDx

on each side of the chip. The

capacitor value should have a value of 0.1 μF and be of a low

ESR type. The total lead length between both ends of the

capacitor and the power supply pin should not exceed 10 mm.

Bypassing between Pin 2 and Pin 8 and between Pin 9 and

Pin 15 should also be considered, unless the ground pair on

each package side is connected close to the package.

BUS1

GND

DD1

PDEN

SPU

UD–

UD+

GND

BUS2

GND

DD2

SPD

DD–

DD+

GND

ADuM4160

BUS1

= 5.0V INPUT

DD1

= 3.3V OUTPUT

BUS2

= 3.3V INPUT

DD2

= 3.3V INPUT

08171-005

Figure 5. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, it

is important to minimize board coupling across the isolation

barrier. Furthermore, design the board layout such that any

coupling that does occur equally affects all pins on a given

component side. Failure to ensure this can cause voltage

differentials between pins exceeding the absolute maximum

ratings of the device, thereby leading to latch-up or permanent

damage.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input

cause narrow (~1 ns) pulses to be sent to the decoder via the

transformer. The decoder is bistable and is, therefore, either set

or reset by the pulses, indicating input logic transitions. In the

absence of logic transitions at the input for more than about

12 USB bit times, a periodic set of refresh pulses indicative of

the correct input state are sent to ensure dc correctness at the

output. If the decoder receives no internal pulses for more than

about 36 USB bit times, the input side is assumed to be unpowered

or nonfunctional, in which case the isolator output is forced to a

default state (see Table 10) by the watchdog timer circuit.

ADuM4160 Data Sheet

Rev. D | Page 12 of 16

The limitation on the magnetic field immunity of the ADuM4160

is set by the condition in which induced voltage in the receiving

coil of the transformer is sufficiently large to either falsely set or

reset the decoder. The following analysis defines the conditions

under which this may occur. The 3 V operating condition of the

ADuM4160 is examined because it represents the most susceptible

mode of operation.

The pulses at the transformer output have an amplitude greater

than 1.0 V. The decoder has a sensing threshold of about 0.5 V, thus

establishing a 0.5 V margin in which induced voltages are tolerated.

The voltage induced across the receiving coil is given by

V = (−dβ/dt)

∑∏r

; n = 1, 2, … , N

where:

β is magnetic flux density (gauss).

N is the number of turns in the receiving coil.

is the radius of the n

turn in the receiving coil (cm).

Given the geometry of the receiving coil in the ADuM4160 and

an imposed requirement that the induced voltage is, at most,

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated, as shown in Figure 6.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kguass)

0.001

100

100M

0.1

0.01

10k 100k 1M 10M

08171-006

Figure 6. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the max-

imum allowable magnetic field of 0.2 kgauss induces a voltage

of 0.25 V at the receiving coil. This is about 50% of the sensing

threshold and does not cause a faulty output transition. Similarly,

if such an event occurs during a transmitted pulse (and is of the

worst-case polarity), it reduces the received pulse from >1.0 V to

0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific

current magnitudes at given distances from the ADuM4160

transformers. Figure 7 expresses these allowable current

magnitudes as a function of frequency for selected distances.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

0.1

0.01

1k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

08171-007

Figure 7. Maximum Allowable Current

for Various Current-to-ADuM4160 Spacings

As shown, the ADuM4160 is extremely immune and can be

affected only by extremely large currents operated at high

frequency very close to the component. For the 1 MHz example

noted, a 0.5 kA current would need to be placed 5 mm away

from the ADuM4160 to affect the operation of the component.

Note that at combinations of strong magnetic field and high

frequency, any loops formed by printed circuit board traces can

induce error voltages sufficiently large enough to trigger the

thresholds of succeeding circuitry. Take care in the layout of

such traces to avoid this possibility.

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period. The rate of

insulation degradation is dependent on the characteristics of the

voltage waveform applied across the insulation. In addition to

the testing performed by the regulatory agencies, Analog

Devices carries out an extensive set of evaluations to determine

the lifetime of the insulation structure within the ADuM4160.

Analog Devices performs accelerated life testing using voltage

levels higher than the rated continuous working voltage. Accele-

ration factors for several operating conditions are determined.

These factors allow calculation of the time to failure at the actual

working voltage. The values shown in Table 8 summarize the

peak voltage for 50 years of service life for a bipolar ac operating

condition, and the maximum CSA/VDE approved working

voltages. In many cases, the approved working voltage is higher

than 50-year service life voltage. Operation at these high work-

ing voltages can lead to shortened insulation life in some cases.

Data Sheet ADuM4160

Rev. D | Page 13 of 16

RATED PEAK VOLTAGE

08171-008

The insulation lifetime of the ADuM4160 depends on the voltage

waveform type imposed across the isolation barrier. The iCoupler

insulation structure degrades at different rates depending on

whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8,

Figure 9, and Figure 10 illustrate these different isolation voltage

waveforms.

Figure 8. Bipolar AC Waveform

RATED PEAK VOLTAGE

08171-009

Bipolar ac voltage is the most stringent environment. The goal

of a 50-year operating lifetime under the ac bipolar condition

determines the Analog Devices recommended maximum

working voltage.

Figure 9. Unipolar AC Waveform

In the case of unipolar ac or dc voltage, the stress on the insula-

tion is significantly lower. This allows operation at higher working

voltages and still achieves a 50-year service life. The working

voltages listed in Table 8 can be applied while maintaining the

50-year minimum lifetime, provided that the voltage conforms

to either the unipolar ac or dc voltage cases. Treat any cross-

insulation voltage waveform that does not conform to Figure 9

or Figure 10 as a bipolar ac waveform and limit its peak voltage

to the 50-year lifetime voltage value listed in Table 8.

RATED PEAK VOLTAGE

08171-010

Figure 10. DC Waveform

Note that the voltage presented in Figure 9 is shown as sinu-

soidal for illustration purposes only. It is meant to represent any

voltage waveform varying between 0 V and some limiting value.

The limiting value can be positive or negative, but the voltage

cannot cross 0 V.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

ADUM4160BRWZ

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