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UJA1161TK,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
UJA1161 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 10 of 27
NXP Semiconductors
UJA1161
Self-supplied high-speed CAN transceiver with Standby mode
It will be switched on again on entering CAN Offline mode when V
BAT
rises above the
undervoltage recovery threshold (V
uvr(CAN)
) and the UJA1161 is no longer in Off/Overtemp
mode. CAN Off mode prevents reverse currents flowing from the bus when the battery
supply to the UJA1161 is lost.
6.3.2 CAN standard wake-up
The UJA1161 monitors the bus for a wake-up pattern when the CAN transceiver is in
Offline mode.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN bus within the wake-up timeout time (t
to(wake)
) to pass the wake-up
filter and trigger a wake-up event (see Figure 5
; note that additional pulses may occur
between the recessive/dominant phases). The recessive and dominant phases must last
at least t
wake(busrec)
and t
wake(busdom)
, respectively.
Pin RXD is driven LOW when a valid CAN wake-up pattern is detected on the bus.
6.4 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage. This will cause the
signal levels on TXD, RXD, STBN and CTS to be adjusted to the I/O levels of the
microcontroller, enabling direct interfacing without the need for glue logic.
6.5 CAN transceiver status pin (CTS)
Pin CTS is driven HIGH to indicate to microcontroller that the transceiver is fully enabled
and data can be transmitted and received via the TXD/RXD pins.
Pin CTS is actively driven LOW:
• while the transceiver is starting up (e.g. during a transition from Standby to Normal
mode) or
• if pin TXD is clamped LOW for t > t
to(dom)TXD
or
• if an undervoltage is detected on VIO or BUF
Fig 5. CAN wake-up timing
t
dom
≥ t
wake(busdom)
recessive
t
rec
≥ t
wake(busrec)
t
dom
≥ t
wake(busdom)
dominant dominant
015aaa267
t
wake
< t
to(wake)
CAN wake-up
UJA1161 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 11 of 27
NXP Semiconductors
UJA1161
Self-supplied high-speed CAN transceiver with Standby mode
6.6 CAN fail-safe features
6.6.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (t
to(dom)TXD
), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
traffic). The TXD dominant time-out timer is reset when pin TXD goes HIGH. The TXD
dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
6.6.2 Pull-up on TXD pin
Pin TXD has an internal pull-up (towards V
IO
) to ensure a safe defined recessive driver
state in case the pin is left floating.
6.6.3 Pull-down on STBN pin
Pin STBN has an internal pull-down (to GND) to ensure the UJA1161 switches to Standby
mode if STBN is left floating.
6.6.4 Loss of power at pin BAT
A loss of power at pin BAT has no impact on the bus lines or on the microcontroller. No
reverse currents flow from the bus.
UJA1161 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 12 of 27
NXP Semiconductors
UJA1161
Self-supplied high-speed CAN transceiver with Standby mode
7. Limiting values
[1] When the device is not powered up, I
BUF(max)
= 25 mA.
[2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b.
[3] ESD performance according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house for pins BAT, CANH and
CANL; the result was equal to or better than 6 kV.
[4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k).
[5] Pins BUF and BAT connected to GND, emulating the application circuit.
[6] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ).
[7] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF).
[8] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T
vj
=T
amb
+P R
th(j-a)
, where R
th(j-a)
is a
fixed value used in the calculation of T
vj
. The rating for T
vj
limits the allowable combinations of power dissipation (P) and ambient
temperature (T
amb
).
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
x
voltage on pin x DC value
pins BUF
[1]
, VIO 0.2 +6 V
pins TXD, RXD, STBN, CTS 0.2 V
IO
+0.2 V
pin BAT 0.2 +40 V
pins CANH and CANL with respect to any
other pin
58 +58 V
V
(CANH-CANL)
voltage between pin CANH
and pin CANL
40 +40 V
V
trt
transient voltage on pins
BAT via reverse polarity diode and capacitor
to ground
CANL, CANH: coupling via 1 nF capacitors
[2]
150 +100 V
V
ESD
electrostatic discharge
voltage
IEC 61000-4-2
[3]
on pins CANH and CANL; pin BAT with
capacitor
6+6 kV
HBM
[4]
on pins CANH, CANL
[5]
8+8 kV
on pin BAT 4+4 kV
on any other pin 2+2 kV
MM
[6]
on any pin 100 +100 V
CDM
[7]
on corner pins 750 +750 V
on any other pin 500 +500 V
T
vj
virtual junction temperature
[8]
40 +150 C
T
stg
storage temperature 55 +175 C
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UJA1161TK,118

Mfr. #:
Buy UJA1161TK,118
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1161TK/HVSON14///REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
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