UJA1161 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 16 of 27
NXP Semiconductors
UJA1161
Self-supplied high-speed CAN transceiver with Standby mode
10. Dynamic characteristics
Table 7. Dynamic characteristics
T
vj
=
40
C to +150
C; V
BAT
= 4.5 V to 28 V; V
IO
=2.85V to 5.5V; R
(CANH-CANL)
= 60
; all voltages are defined with respect
to ground; positive currents flow into the IC; typical values are given at V
BAT
= 13 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Voltage sources; pins BUF and VIO
t
startup
start-up time from V
BAT
exceeding the power-on
detection threshold until V
BUF
>
90 % undervoltage threshold;
C
BUF
=4.7F
-2.84.7ms
t
d(uvd)
undervoltage detection delay time 6 - 54 s
Mode control: pin STBN
t
fltr(stb)
standby filter time 2.5 - 13.5 s
CAN transceiver timing; pins CANH, CANL, TXD and RXD
t
d(TXD-RXD)
delay time from TXD to RXD R
L
=60; C
L
= 100 pF;
50 % V
TXD
to 50 % V
RXD
;
C
RXD
= 15 pF;
f
TXD
= 250 kHz
--255ns
R
L
= 120 ; C
L
=200 pF;
50 % V
TXD
to 50 % V
RXD
;
C
RXD
= 15 pF;
f
TXD
= 250 kHz
[1]
--350ns
t
d(TXD-busdom)
delay time from TXD to bus dominant - 80 - ns
t
d(TXD-busrec)
delay time from TXD to bus recessive - 80 - ns
t
d(busdom-RXD)
delay time from bus dominant to RXD C
RXD
= 15 pF - 105 - ns
t
d(busrec-RXD)
delay time from bus recessive to RXD C
RXD
= 15 pF - 120 - ns
t
bit(RXD)
bit time on pin RXD t
bit(TXD)
= 500 ns
[2]
400 - 550 ns
t
wake(busdom)
bus dominant wake-up time first pulse (after first recessive) for
wake-up on pins CANH and CANL;
CAN Offline mode
0.5 - 3.0 s
second pulse for wake-up on pins
CANH and CANL
0.5 - 3.0 s
t
wake(busrec)
bus recessive wake-up time first pulse for wake-up on pins
CANH and CANL;
CAN Offline mode
0.5 - 3.0 s
second pulse (after first dominant)
for wake-up on pins CANH and
CANL
0.5 - 3.0 s
t
to(wake)
wake-up time-out time between first and second dominant
pulses; CAN Offline mode
570 - 1200 s
t
to(dom)TXD
TXD dominant time-out time CAN Active mode;
V
TXD
= 0 V
2.7 - 3.3 ms
t
to(silence)
bus silence time-out time recessive time measurement started
in all CAN modes; R
L
= 120
0.95 - 1.17 s
t
d(busact-bias)
delay time from bus active to bias - - 200 s
t
startup(CAN)
CAN start-up time when switching to Active mode
(CTS = HIGH)
--220s
UJA1161 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 17 of 27
NXP Semiconductors
UJA1161
Self-supplied high-speed CAN transceiver with Standby mode
[1] Guaranteed by design.
[2] See Figure 7
.
Fig 6. CAN transceiver timing diagram
Fig 7. Loop delay symmetry timing diagram
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UJA1161 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 17 April 2014 18 of 27
NXP Semiconductors
UJA1161
Self-supplied high-speed CAN transceiver with Standby mode
11. Application information
11.1 Application diagram
(1) Actual capacitance value must be a least 1.76 F with 5 V DC offset (recommended capacitor value is 4.7 F)
(2) For bus line end nodes, R
T
= 60 in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’
termination of e.g. R
T
= 1.3 k can be used, if required by the OEM.
Fig 8. Typical application using the UJA1161
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UJA1161TK,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1161TK/HVSON14///REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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