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MAX1060AEEI+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 7
2.48
2.49
2.51
2.50
2.52
2.53
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1060/64 toc10
V
DD
(V)
V
REF
(V)
4.50 5.004.75 5.25 5.50
2.48
2.49
2.51
2.50
2.52
2.53
-40 10-15 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1060/64 toc11
TEMPERATURE (°C)
V
REF
(V)
1.0
0.5
0
-0.5
-1.0
4.50 5.004.75 5.25 5.50
OFFSET ERROR
vs. SUPPLY VOLTAGE
MAX1060/64 toc12
V
DD
(V)
OFFSET ERROR (LSB)
1.0
0.5
0
-0.5
-1.0
-40 10-15 35 60 85
OFFSET ERROR
vs. TEMPERATURE
MAX1060/64 toc13
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-0.50
0
-0.25
0.25
0.50
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1060/64 toc14
V
DD
(V)
GAIN ERROR (LSB)
4.50 5.004.75 5.25 5.50
0
0.125
0.250
0.375
0.500
GAIN ERROR vs. TEMPERATURE
MAX1060/64 toc15
TEMPERATURE (°C)
GAIN ERROR (LSB)
-40 35 60-15 10 85
50
150
100
200
250
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1060/64 toc16
V
DD
(V)
I
LOGIC
(µA)
4.50 5.004.75 5.25 5.50
Typical Operating Characteristics (continued)
(V
DD
= V
LOGIC
= +5V, V
REF
= +2.500V, f
CLK
= 7.6MHz, C
L
= 20pF, T
A
= +25°C, unless otherwise noted.)
0
50
150
100
200
250
-40 10-15 35 60 85
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
MAX1060/64 toc17
TEMPERATURE (°C)
I
LOGIC
(µA)
-140
-120
-100
-80
-60
-40
-20
0
20
0 400200 600 800 1000 1200
FFT PLOT
MAX1060/64 toc18
FREQUENCY (kHz)
AMPLITUDE (dB)
V
DD
= 5V
f
IN
= 50kHz
f
SAMPLE
= 400ksps
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
8 _______________________________________________________________________________________
Pin Description
NAME FUNCTION
1 HBEN
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
PIN
2 D7 Tri-State Digital I/O Line (D7)
3 D6 Tri-State Digital I/O Line (D6)
4 D5 Tri-State Digital I/O Line (D5)
5 D4 Tri-State Digital I/O Line (D4)
6 D3 Tri-State Digital I/O Line (D3)
7 D2 Tri-State Digital I/O Line (D2)
8 D1/D9 Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
9 D0/D8 Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
10
INT INT goes low when the conversion is complete and the output data is ready.
11
RD
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the
data bus.
12
WR
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
13 CLK
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In inter-
nal clock mode, connect this pin to either V
DD
or GND.
14
CS Active-Low Chip Select. When CS is high, digital outputs (D7–D0) are high impedance.
15 CH7 Analog Input Channel 7
16 CH6 Analog Input Channel 6
17 CH5 Analog Input Channel 5
18 CH4 Analog Input Channel 4
19 CH3 Analog Input Channel 3
20 CH2 Analog Input Channel 2
21 CH1 Analog Input Channel 1
22 CH0 Analog Input Channel 0
23 COM
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5 LSB during conversion.
24 GND Analog and Digital Ground
25 REFADJ
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01µF
capacitor. When using an external reference, connect REFADJ to V
DD
to disable the internal
bandgap reference.
26 REF
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND
when using the internal reference.
27 V
DD
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
28 V
LOGIC
Digital Power Supply. V
LOGIC
powers the digital outputs of the data converter and can range
from +2.7V to (V
DD
+ 300mV).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
—
—
—
—
15
16
17
18
19
20
21
22
23
24
MAX1060 MAX1064
MAX1060/MAX1064
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 9
Detailed Description
Converter Operation
The MAX1060/MAX1064 ADCs use a successive-
approximation (SAR) conversion technique and an
input track-and-hold (T/H) stage to convert an analog
input signal to a 10-bit digital output. Their parallel (8 + 2)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1060/MAX1064.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuits in
Figures 3a and 3b. In single-ended mode, IN+ is inter-
nally switched to channels CH0–CH7 for the MAX1060
(Figure 3a) and to CH0–CH3 for the MAX1064 (Figure
3b), while IN- is switched to COM (Table 3). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 4).
In differential mode, IN- and IN+ are internally switched to
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. At
the end of the acquisition interval, the T/H switch
opens, retaining the charge on C
HOLD
as a sample of
the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node zero to 0V within
the limits of 10-bit resolution. This action is equivalent to
transferring a 12pF [(V
IN+
) - (V
IN-
)] charge from C
HOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
T/H
TRI-STATE, BIDIRECTIONAL
I/O INTERFACE
10
17kΩ
8
8
2
8
2
8
SUCCESSIVE-
APPROXIMATION
REGISTER
MUX
( ) ARE FOR MAX1060 ONLY.
CHARGE REDISTRIBUTION
10-BIT DAC
CLOCK
ANALOG
INPUT
MULTIPLEXER
CONTROL LOGIC
AND
LATCHES
REF REFADJ
1.22V
REFERENCE
D0–D7
8-BIT DATA BUS
(CH5)
(CH4)
CH3
CH2
CH1
CH0
COM
CLK
CS
WR
RD
INT
V
DD
GND
V
LOGIC
MAX1060
MAX1064
A
V
=
2.05
COMP
HBEN
(CH7)
(CH6)
Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1060/MAX1064
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MAX1060AEEI+

Mfr. #:
Buy MAX1060AEEI+
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 5V 10Bit 8Ch 400ksps w/2.5V Ref & Prl Int
Lifecycle:
New from this manufacturer.
Delivery:
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