ADP4100
http://onsemi.com
12
through a resistor, R
B
, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 100 mA to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
Output Current Sensing
The ADP4100 provides a dedicated Current−Sense
Amplifier (CSA) to monitor the total output current for
proper voltage positioning vs. load current, for the IMON
output and for current−limit detection. Sensing the load
current at the output gives the total real time current being
delivered to the load, which is an inherently more accurate
method than peak current detection or sampling the current
across a sense element such as the low−side MOSFET. This
amplifier can be configured several ways, depending on the
objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lowest cost.
• Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor
temperature.
• Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF
pin, which is connected to the average output voltage. The
inputs to the amplifier are summed together through
resistors from the sensing element, such as the switch node
side of the output inductors, to the inverting input CSSUM.
The feedback resistor between CSCOMP and CSSUM sets
the gain of the amplifier and a filter capacitor is placed in
parallel with this resistor. The gain of the amplifier is
programmable by adjusting the feedback resistor. This
difference signal is used internally to offset the VID DAC
for voltage positioning.
The difference between CSREF and CSCOMP is used as
a differential input for the current−limit comparator.
To provide the best accuracy for sensing current, the CSA
is designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors to make it
extremely accurate.
Current−Limit Setpoint
The current limit threshold on the ADP4100 is
programmed by a resistor between the I
LIMFS
pin and the
CSCOMP pin. The I
LIMFS
current, I
ILIMFS
, is compared
with an internal current reference of 22 mA. If I
ILIMFS
exceeds 22 mA then the output current has exceeded the limit
and the current limit protection is tripped.
I
ILIMFS
+
V
ILIMFS
* V
CSCOMP
R
ILIMFS
(eq. 2)
Where: V
ILIMFS
= V
CSREF
I
ILIMFS
+
V
CSREF
* V
CSCOMP
R
ILIMFS
V
CSREF
* V
CSCOMP
+
R
CS
R
PH
R
L
I
LOAD
(eq. 3)
Where: R
L
= DCR of the Inductor
Assuming that:
R
CS
R
PH
R
L
+ 1mW
(eq. 4)
i.e. the external circuit is set up for a 1 mW Loadline then the
R
ILIMFS
is calculated as follows:
I
ILIMFS
+
1mW I
LOAD
R
LIMITS
(eq. 5)
Assuming we want a current limit of 150 A that means that
I
LIMFS
must equal 22 mA at that load.
22 mA +
1mW 150 A
R
LIMITFS
(eq. 6)
Solving this equation for R
LIMITFS
we get 6.8 kW. Closest
1% resistor is 6.81 kW.
Current−Limit, Short−Circuit and Latchoff Protection
If the current limit is reached and TD5 has completed, an
internal latchoff delay time will start, and the controller will
shut down if the fault is not removed. This delay is four times
longer than the delay time during the startup sequence. The
current limit delay time only starts after the TD5 has
completed. If there is a current limit during startup, the
ADP4100 will go through TD1 to TD5, and then start the
latchoff time. Because the controller continues to cycle the
phases during the latchoff delay time, if the short is removed
before the timer is complete, the controller can return to
normal operation.
The latchoff function can be reset by either removing and
reapplying the supply voltage to the ADP4100, or by
toggling the EN pin low for a short time.
During startup when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit limits the internal COMP
voltage to the PWM comparators to 1.5 V. This limits the
voltage drop across the low−side MOSFETs through the
current balance circuitry. Typical overcurrent latchoff
waveforms are shown in Figure 9).
