ADP4100JCPZ-REEL Datasheet LS2A4KC, ADP4101JCPZ-RL7, ADP4101JCPZ-REEL | P13-P15

ADP4100

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Figure 9. Overcurrent Latchoff Waveforms

Channel 1: CSREF, Channel 2: COMP,

Channel 3: PWM1

An inherent per phase current limit protects individual

phases if one or more phases stops functioning because of a

faulty component. This limit is based on the maximum

normal mode COMP voltage.

Output Current Monitor

IMON is an analog output from the ADP4100

representing the total current being delivered to the load. It

outputs an accurate current that is directly proportional to

the current set by the ILIMFS resistor.

(eq. 7)

IMON

+ 10 I

LIMFS

The current is then run through a parallel RC connected

from the I

MON

pin to the FBRTN pin to generate an

accurately scaled and filtered voltage as per the VR11.1

specification. The size of the resistor is used to set the I

MON

scaling.

The scaling is set such that I

MON

= 900 mV at the TDC

current of the processor. This means that the RIMON

resistor should be chosen as follows.

From the Current−Limit Setpoint paragraph we know the

following:

(eq. 8)

ILIMFS

1mW I

LOAD

LIMFS

IMON

+ 10

1mW I

LOAD

LIMFS

For a 150 A current limit R

LIMFS

= 6.81 kW. Assuming the

TDC = 135 A then V

MON

should equal 900 mV when

LOAD

= 135 A.

When I

LOAD

= 135 A, I

MON

equals:

(eq. 9)

MON

+ 10

1mW 135 A

6.81 kW

+ 198mA

IMON

+ 900 mV + 198 mA R

MON

This gives a value of 4.54 kW for RMON.

If the TDC and OCP limit for the processor have to be

changed then it may be necessary to change the ILIMITFS

resistor only. This is because the ILIMITFS resistor sets up

both the current limit and also the current out of the IMON

pin, as explained earlier.

The I

MON

pin also includes an active clamp to limit the

IMON voltage to 1.15 V MAX while maintaining accuracy

at 900 mV full scale.

Active Impedance Control Mode

For controlling the dynamic output voltage droop as a

function of output current, the CSA gain and load line

programming can be scaled to be equal to the droop

impedance of the regulator times the output current. This

droop voltage is then used to set the input control voltage to

the system. The droop voltage is subtracted from the DAC

reference input voltage directly to tell the error amplifier

where the output voltage should be. This allows enhanced

feed−forward response.

Load Line Setting

For load line values greater than 1 mW, R

CSA

can be set

equal to R

, and the LLSET pin can be directly connected

to the CSCOMP pin. When the load line value needs to be

less than 1 mW, two additional resistors are required.

Figure 10 shows the placement of these resistors.

Figure 10. Load Line Setting Resistors

CSSUM

CSCOMP

CSREF

ADP4100

LLSET

OPTIONAL LOAD LINE

SELECT SWITCH

LL2

LL1

The two resistors R

LL1

and R

LL2

set up a divider between

the CSCOMP pin and CSREF pin. This resistor divider is

input into the LLSET pin to set the load line slope R

of the

according to the following equation:

(eq. 10)

LL2

LL1

) R

LL2

CSA

The resistor values for R

LL1

and R

LL2

are limited by two

factors.

• The minimum value is based upon the loading of the

CSCOMP pin. This pin’s drive capability is 500 mA

and the majority of this should be allocated to the CSA

feedback. If the current through R

LL1

and R

LL2

is limited

to 10% of this (50 mA), the following limit can be placed

for the minimum value for R

LL1

and R

LL2

ADP4100

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(eq. 11)

LL1

) R

LL2

LIM

CSA

50 10

Here, I

LIM

is the current−limit current, which is the

maximum signal level that the CSA responds to.

• The maximum value is based upon minimizing induced

dc offset errors based on the bias current of the LLSET

pin. To keep the induced dc error less than 1 mV, which

makes this error statistically negligible, place the

following limit of the parallel combination of R

LL1

and R

LL2

It is best to select the resistor values to minimize their

values to reduce the noise and parasitic susceptibility of the

feedback path.

(eq. 12)

LL1

LL2

LL1

) R

LL2

1 10

120 10

+ 8.33 kW

By combining Equation 10 with Equation 12 and selecting

minimum values for the resistors, the following equations

result:

(eq. 13)

LL2

LIM

50 mA

(eq. 14)

LL1

CSA

* 1

LL2

Therefore, both R

LL1

and R

LL2

need to be in parallel and

less than 8.33 kW.

Another useful feature for some VR applications is the

ability to select different load lines. Figure 10 shows an

optional MOSFET switch that allows this feature. Here,

design for R

CSA

= R

O(MAX)

(selected with Q

on) and then

use Equation 10 to set R

= R

O(MIN)

(selected with Q

off).

For this design, R

CSA

= R

= 1 mW. As a result, connect

LLSET directly to CSCOMP; the R

LL1

Current Control Mode and Thermal Balance

The ADP4100 has individual inputs (SW1 to SW6) for

each phase that are used for monitoring the current of each

phase. This information is combined with an internal ramp

to create a current balancing feedback system that has been

optimized for initial current balance accuracy and dynamic

thermal balancing during operation. This current balance

information is independent of the average output current

information used for positioning.

The magnitude of the internal ramp can be set to optimize

the transient response of the system. It also monitors the

supply voltage for feed−forward control for changes in the

supply. A resistor connected from the power input voltage

to the RAMPADJ pin determines the slope of the internal

PWM ramp.

Voltage Control Mode

A high gain, high bandwidth, voltage mode error

amplifier is used for the voltage mode control loop. The

control input voltage to the positive input is set via the VID

logic according to the voltages listed in VID Code Table.

The VID code is set using the VID Input pins.

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location

with Resistor R

and is used for sensing and controlling the

output voltage at this point. A current source (equal to

16 mA) from the FB pin flowing through R

is used for

setting the no load offset voltage from the VID voltage. The

no load voltage is negative with respect to the VID DAC for

Intel CPU’s.

The value of R

can be found using the following

equation:

(eq. 15)

VID

* V

ONL

RAMPADJ Input Current

The resistor connected to the Rampadj pin sets the internal

PWM ramp. The value for this resistor is chosen to provide

the combination of thermal balance, stability and transient

response.

(eq. 16)

3 A

Where

is the internal ramp amplifier gain (= 0.5)

is the current balancing amplifier gain (= 5)

is the total low side MOSFET on resistance

is the internal ramp capacitor value (= 5pF).

The internal ramp voltage can be calculated as follows:

(eq. 17)

(1 * D) V

VID

The size of the internal ramp can be made larger or

smaller. If it is made larger, stability and noise rejection

improves but the transient performance decreases. If the

ramp is made smaller then the transient response improves

however noise rejection and stability degrades.

COMP Pin Ramp

There is a ramp signal on the COMP signal, which is due

to the droop voltage and the output voltage ramps. This ramp

adds to the internal ramp to produce the following ramp

signal at the PWM input.

(eq. 18)

1 *

2 (1*n D)

n f

Where Cx = bulk capacitance

= Droop

n = number of phases

= switching frequency per phase

D = duty cycle

= Internal Ramp Voltage (calculated in

Rampadj section of this data sheet)

ADP4100

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This ramp voltage should be set to at least 0.5 V for noise

immunity reasons. If it is less than 0.5 V then decrease the

ramp resistor.

Dynamic VID

The ADP4100 has the ability to respond to dynamically

changing VID inputs while the controller is running. This

allows the output voltage to change while the supply is

running and supplying current to the load. This is commonly

referred to as Dynamic VID (DVID). A DVID can occur

under either light or heavy load conditions. The processor

signals the controller by changing the VID inputs in a single

or multiple steps from the start code to the finish code. This

change can be positive or negative.

When a VID bit changes state, the ADP4100 detects the

change and ignores the DAC inputs for a minimum of

200 ns. This time prevents a false code due to logic skew

while the VID inputs are changing. Additionally, the first

VID change initiates the PWRGD and CROWBAR

blanking functions for a minimum of 100 ms to prevent a

false PWRGD or CROWBAR event. Each VID change

resets the internal timer.

If a VID off code is detected the ADP4100 will wait for

5 msec to ensure that the code is correct before initiating a

shutdown of the controller.

Enhanced Transients Mode

The ADP4100 incorporates enhanced transient response

for both load step up and load release. For load step up it

senses the output of the error amp to determine if a load step

up has occurred and then sequences on the appropriate

number of phases to ramp up the output current.

For load release, it also senses the output of the error amp

and uses the load release information to trigger the TRDET

pin, which is then used to adjust the error amp feedback for

optimal positioning. This is especially important during

high frequency load steps.

Additional information is used during load transients to

ensure proper sequencing and balancing of phases during

high frequency load steps as well as minimizing the stress on

components such as the input filter and MOSFETs.

TRDET and Phase Shuffling

The ADP4100 senses the error amp output and triggers the

TRDET pin when a load release takes place. The TRDET

circuit, as shown in Figure 2, adjusts the feedback for

optimal positioning especially during high frequency load

steps. TRDET is also used to trigger phase shuffling. If

repeated transients take place at the switching frequency

then its possible for one phase to carry most of the currrent.

To prevent this from happening the ADP4100 will shuffle

the phases whenever a load release happens, i.e. it will

randomize the phase sequence.

Reference Current

The IREF pin is used to set an internal current reference.

This reference current sets I

and I

TTSENSE

. A resistor to

ground programs the current based on the 1.8 V output.

(eq. 19)

REF

1.8 V

IREF

Typically, R

IREF

is set to 121 kW to program IREF = 15 mA.

The following currents are then equal to:

(eq. 20)

+ I

REF

+ 15 mA

TTSENSE

+ −8(I

IREF

) + −120 mA

Power Good Monitoring

The power good comparator monitors the output voltage

via the CSREF pin. The PWRGD pin is an open−drain

output whose high level (when connected to a pullup

resistor) indicates that the output voltage is within the

nominal limits specified in the specifications above based on

the VID voltage setting. PWRGD goes low if the output

voltage is outside of this specified range, if the VID DAC

inputs are in no CPU mode, or whenever the EN pin is pulled

low. PWRGD is blanked during a DVID event for a period

of 100 ms to prevent false signals during the time the output

is charging.

The PWRGD circuitry also incorporates an initial turn−on

delay time (TD5). Prior to the SS voltage reaching the

programmed VID DAC voltage and the PWRGD masking

time finishing, the PWRGD pin is held low. Once the SS

circuit reaches the programmed DAC voltage, the internal

timer operates.

The range for the PWRGD comparator is +300 mV and

−500 mV.

Power State Indicator

The PSI pin is an input used to determine the operating

state of the load. If this input is pulled low, the load is in a low

power state and the controller asserts the ODN

pin low,

which can be used to disable phases and maintain better

efficiency at lighter loads.

The sequencing into and out of low power operation is

maintained to minimize output deviations as well as

providing full power load transients immediately after

exiting a low power state.

The user can program if one or two phases are enabled

during PSI

using the PSI_SET pin. If this pin is pulled low

then 1 phase is enabled (always phase 1). If it is pulled high

then two phases are enabled (phase 1 and phase 4 in a

6−phase or 5−phase system, phase 1 and phase 3 in a 4−phase

system. Extreme care should be taken to ensure that OD1

connected to all phases enabled during PSI

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

ADP4100JCPZ-REEL

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Manufacturer:

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Description:

Voltage Regulators - Switching Regulators VR11.1 6PH CTRL W/PMBUS ITF

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ADP4100JCPZ-REEL

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