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ADP4100JCPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ADP4100
http://onsemi.com
4
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage Range (Note 1) V
IN
−0.3 to 6 V
FBRTN V
FBRTN
−0.3 to + 0.3 V V
PWM2 to PWM6, Rampadj −0.3 to V
IN
+ 0.3 V
SW1 to SW6 −5 to +25 V V
SW1 to SW6 (<200 ns|) −10 to +25 V V
All other Inputs and Outputs −0.3 to V
IN
+ 0.3 V
Storage Temperature Range TSTG −65 to 150 °C
Operating Ambient Temperature Range 0 to 85 °C
ESD Capability, Human Body Model (Note 2) ESD
HBM
2 kV
ESD Capability, Machine Model (Note 2) ESD
MM
100 V
Moisture Sensitivity Level MSL 3 −
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
T
SLD
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to Electrical Characteristics and Application Information for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
3. For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Characteristics, LFCSP, 7mm * 7mm (Note 1)
Thermal Resistance, Junction−to−Air (Note 4)
Thermal Resistance, Junction−to−Lead 2 (Note 4)
R
q
JA
R
Y
JL
24
10
°C/W
4. Values based on copper area of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 1)
Characteristic
Symbol Min Max Unit
Output Voltage (Note 5) V
OUT
0.375 1.6 V
Ambient Temperature T
A
0 85 °C
5. Maximum limit for V
OUT
= V
OUT(NOM)
− 10%.
ADP4100
http://onsemi.com
5
PIN ASSIGNMENT
Pin No. Pin Name Description
1 NC No Connect
2 NC No Connect
3 NC No Connect
4 NC No Connect
5 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
6 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
7 PSI_SET This input sets the number of phases enabled during PSI. Pulling this input high means that two phases,
Phases 1 and Phase 4 (when 6 phases are enabled during normal operation), are enabled during PSI
.
Grounding this pin means only Phase 1 is enabled during PSI.
8 LLSET Output Loadline Programming Input. This pin can be connected directly to CSCOMP or it can be connected to
the centerpoint of a resistor divider between CSCOMP and CSREF. Connecting LLSET to CSREF disables
the loadline.
9 IMON Total Current Output Pin.
10 TTSENSE VR Temperature Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the
temperature at the desired thermal monitoring point.
11 VRHOT VR HOT Output. Open drain output that signals when the temperature at the monitoring point connected to
TTSENSE exceeds the VRHOT temperature threshold.
12 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for I
FB
,
IILIMFS, and ITH(X).
13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
15 TRDET Transient Detect. This output is asserted low whenever a load release is detected
16 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
17 COMP Error Amplifier Output and Compensation Point.
18 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no load offset point.
19 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power−good and crowbar functions. This pin should be connected to the common point of
the output inductors.
20 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
21 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of
the current sense amplifier and the positioning loop response time.
22 ILIMFS Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal current
sensing signal for current−limit and IMON.
23 ODN Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low, otherwise it
functions in the same way as OD1
.
24 OD1 Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when V
CC
is below its
UVLO threshold to signal to the Driver IC that the driver high−side and low−side outputs should go low.
25 to 30 SW6 to
SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
31 to 36 PWM6 to
PWM1
Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3121. Connecting PWM6 to V
CC
disables PWM6, connecting PWM5 to V
CC
disables PWM5 and PWM6,
etc. This means the ADP4100 can be setup to operate as a 1− 2−, 3−, 4−, 5−, or 6−phase controller.
37 V
CC
Supply Voltage for the Device. A 340 W resistor should be placed between the 12 V system supply and the
V
CC
pin. The internal shunt regulator maintains V
CC
= 5.0 V.
38 to 45 VID7 to
VID0
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open.
When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 V.
46 PSI Power State Indicator. Pulling this pin low places the controller in lower power state operation.
47 PWRGD Power−Good Output. Open−drain output that signals when the output voltage is outside of the proper
operating range.
48 VCC3 3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3V LDO.
ADP4100
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS
V
in
= (5.0 V) FBRTN − GND, for typical values T
A
= 25°C, for min/max values T
A
= 0°C to 85°C; unless otherwise noted.
Parameter
Test Conditions Symbol Min Typ Max Unit
Reference Current
Reference Bias Voltage V
IREF
1.75 1.8 1.85 V
Reference Bias Current
R
IREF
= 121 kW
I
IREF
15
mA
Error Amplifier
Output Voltage Range (Note 6) V
COMP
0 4.4 V
Accuracy Relative to nominal DAC output, referenced to
FBRTN (see Figure 4)
In startup
V
FB
V
FB(BOOT)
7
1.093
1.1
7
1.107
mV
V
Load Line Positioning Accuracy −77 −80 −83 mV
LLSET Input Voltage Range −250 250 mV
LLSET Input Bias Current −10 10 nA
Differential Non−linearity −1.0 +1.0 LSB
Input Bias Current
R
IREF
= 121 kW
I
FB
14.2 16 17.7
mA
FBRTN Current I
FBRTN
100 200
mA
Output Current FB forced to V
OUT
−3% I
COMP
500
mA
Gain Bandwidth Product COMP = FB GBW
(ERR)
20 MHz
Slew Rate COMP = FB 25
V/ms
BOOT Voltage Hold Time Internal Timer t
BOOT
2.0 ms
VID Inputs
Input Low Voltage VID(X) V
IL(VID)
0.3 V
Input High Voltage VID(X) V
IH(VID)
0.8 V
Input Current I
IN(VID)
−5.0
mA
VID Transition Delay Time (Note 6) VID code change to FB change 200 ns
No CPU Detection Turn−Off Delay
Time (Note 6)
VID code change to PWM going low 5.0
ms
Oscillator
Frequency Range (Note 6)
f
OSC
0.25 9.0 MHz
Frequency Variation
T
A
= 25°C, R
T
= 270 kW, 6−phase
T
A
= 25°C, R
T
= 130 kW, 6−phase
T
A
= 25°C, R
T
= 68 kW, 6−phase
f
PHASE
225 245
500
850
265 kHz
Output Voltage
RT = 500 kW to GND
V
RT
1.93 2.03 2.13 V
RAMPADJ Output Voltage
RAMPADJ − FB, V
FB
= 1V, IRAMPADJ = −60 mA
V
RAMPADJ
−50 +50 mV
RAMPADJ Input Current Range I
RAMPADJ
5.0 60
mA
Current Sense Amplifier
Offset Voltage
CSSUM − CSREF (see Figure 5) V
OS(CSA)
−1.0 +1.0 mV
Input Bias Current, CSREF CSREF = 1.0 V I
BIAS(CSREF)
−20 +20
mA
Input Bias Current, CSSUM CSREF = 1.0 V I
BIAS(CSSUM)
−10 +10 nA
Gain Bandwidth Product CSSUM = CSCOMP GBW
(CSA)
10 MHz
Slew Rate C
CSCOMP
= 10pF 10
V/ms
Input Common−Mode Range CSSUM and CSREF 0 3.0 V
Output Voltage Range 0.05 3.0 V
Output Current I
CSCOMP
500
mA
Current−Limit Latchoff Delay time Internal Timer 8.0 ms
6. Guaranteed by design or bench characterization, not tested in production.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

ADP4100JCPZ-REEL

Mfr. #:
Buy ADP4100JCPZ-REEL
Manufacturer:
ON Semiconductor
Description:
Voltage Regulators - Switching Regulators VR11.1 6PH CTRL W/PMBUS ITF
Lifecycle:
New from this manufacturer.
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