MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
4 _______________________________________________________________________________________
t
TR
10 40
nsC
LOAD
= 20pF, Figure 1
RD Rise to Output Disable
WR to CLK Fall Setup Time
t
CWS
60
ns
nsCLK Pulse Width High
nsCLK Period
t
CH
40
RD Fall to Output Data Valid
t
DO
10 50
ns
RD Fall to INT High Delay
t
INT1
50
ns
CS Fall to Output Data Valid
t
DO2
100
ns
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
t
CP
132
CLK Pulse Width Low t
CL
40
ns
Data Valid to WR Rise Time
t
DS
40
ns
WR Rise to Data Valid Hold Time
t
DH
0
ns
CLK Fall to WR Hold Time
t
CWH
40
ns
CS to CLK or WR Setup Time
t
CSWS
40
ns
CLK or WR to CS Hold Time
t
CSWH
0
ns
CS Pulse Width
t
CS
100
ns
WR Pulse Width (Note 8)
t
WR
60
ns
t
TC
10 60
nsC
LOAD
= 20pF, Figure 1
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
CS Rise to Output Disable
Note 1: Tested at V
DD
= +5V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
DD
.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS
(V
DD
= +5V ±10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 7.6MHz (50% duty cycle),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
