MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 7
Pin Description
D01010
INT
1111
RD
1212
WR
1313
CLK1414
D466
D377
D288
D199
D555
D644
1
D733
D822
D9
1
Three-State Digital I/O Line (D0)
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read
operation on the data bus.
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either V
DD
or GND.
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D7)
Three-State Digital Output (D8)
Three-State Digital Output (D9)
GND1923
REFADJ2024
CH219
CH11620
CH01721
COM1822
CH318
CH417
CH516
CS
1515
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01µF capacitor. When using an external reference, connect REFADJ to V
DD
to
disable the internal bandgap reference.
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high
impedance.
PIN
MAX1296MAX1294
NAME FUNCTION
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
8 _______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1296
REF
2125
MAX1294
NAME
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.
FUNCTION
26 22 V
DD
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
27 23 D11 Three-State Digital Output (D11)
28 24 D10 Three-State Digital Output (D10)
_______________Detailed Description
Converter Operation
The MAX1294/MAX1296 ADCs use a successive-approx-
imation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal to
a 12-bit digital output. This output format provides easy
interface to standard microprocessors (µPs). Figure 2
shows the simplified internal architecture of the MAX1294/
MAX1296.
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
12
17k
12
SUCCESSIVE-
APPROXIMATION
REGISTER
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
ANALOG
INPUT
MULTIPLEXER
CONTROL LOGIC
&
LATCHES
REF REFADJ
1.22V
REFERENCE
D0D11
12-BIT DATA BUS
(CH5)
(CH4)
(CH3)
(CH2)
CH1
CH0
COM
CLK
CS
( ) ARE FOR MAX1294 ONLY.
WR
RD
INT
V
DD
GND
MAX1294
MAX1296
A
V
=
2.05
COMP
Figure 2. Simplified Functional Diagram
MAX1294/MAX1296
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________ 9
BIT
PD1, PD0
0
D7, D6
PD1 and PD0 select the various clock and power-down modes.
Full Power-Down Mode. Clock mode is unaffected.
D5 ACQMOD
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
NAME FUNCTIONAL DESCRIPTION
0
10
Standby Power-Down Mode. Clock mode is unaffected.
0
11
Normal Operation Mode. External clock mode selected.
1
Normal Operation Mode. Internal clock mode selected.
D4
SGL/DIF
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2, 4).
D3
UNI/BIP
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V
REF
can be converted; in bipolar mode, the
signal can range from -V
REF
/2 to +V
REF
/2.
D2, D1, D0 A2, A1, A0
Address bits A2, A1, A0 select which of the 6/2 (MAX1294/MAX1296) channels is to be converted
(see Tables 2, 3).
Table 1. Control-Byte Functional Description
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADCs’ analog com-
parator is illustrated in the equivalent input circuits of
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1294
(Figure 3a) and to CH0–CH1 for the MAX1296 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
the analog inputs. This configuration is pseudo-differen-
tial to the effect that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5
LSB (±0.1 LSB for best performance) with respect to
GND during a conversion. To accomplish this, connect
a 0.1µF capacitor from IN- (the selected input) to GND.
Figure 3a. MAX1294 Simplified Input Structure Figure 3b. MAX1296 Simplified Input Structure
CH0
CH1
CH3
CH2
CH5
CH4
COM
C
SWITCH
TRACK
T/H
SWITCH
R
IN
800
C
HOLD
HOLD
12-BIT CAPACITIVE DAC
V
REF
ZERO
COMPARATOR
+
12pF
SINGLE-ENDED MODE: IN+ = CH0CH5, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
CH0
CH1
COM
C
SWITCH
TRACK
T/H
SWITCH
R
IN
800
C
HOLD
HOLD
12-BIT CAPACITIVE DAC
V
REF
ZERO
COMPARATOR
+
12pF
SINGLE-ENDED MODE: IN+ = CH0CH1, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX

MAX1294BCEI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 6Ch 420ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
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