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83947AYI-147LF

P1-P3P4-P6P7-P9P10-P12
Low Skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer
83947I-147
Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20161
GENERAL DESCRIPTION
The 83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL
Fanout Buffer. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50 series or parallel terminated
transmission lines. The effective fanout can be increased from
9 to 18 by utilizing the ability of the outputs to drive two series
terminated lines.
Guaranteed output and part-to-part skew characteristics make
the 83947I-147 ideal for high performance, 3.3V or 2.5V single
ended applications.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
• Nine LVCMOS/LVTTL outputs
• Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
• Maximum output frequency: 250MHz
• Output skew: 115ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
GND
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
V
DD
GND
GND
Q6
V
DDO
Q7
GND
Q8
V
DDO
GND
GND
Q2
V
DDO
Q1
GND
Q0
V
DDO
GND
ICS83947I-147
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Number Name Type Description
1, 8, 9, 12, 16, 17, 20,
24, 25, 29, 32
GND Power Power supply ground.
2 CLK_SEL Input Pullup
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
3, 4 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels.
7V
DD
Power Core supply pin.
10, 14, 18, 22, 27, 31 V
DDO
Power Output supply pins.
11, 13, 15, 19, 21, 23,
26, 28, 30
Q8, Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Q0 thru Q8 clock outputs.
LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Control Inputs Output
OE CLK_EN Q0:Q8
0 X Hi-Z
1 0 LOW
1 1 Follows CLK input
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
12 pF
R
PULLUP
Input Pullup Resistor 51 KΩ
R
OUT
Output Impedance 7
Ω
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20163
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±0.3V OR 2.5V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage
3.0 3.3 3.6 V
2.375 2.5 2.625 V
V
DDO
Output Supply Voltage
3.0 3.3 3.6 V
2.375 2.5 2.625 V
I
DD
Input Supply Current 50 mA
I
DDO
Output Supply Current 9mA
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage
CLK0, CLK1 -0.3 1.3 V
CLK_SEL, CLK_EN, OE -0.3 0.8 V
I
IH
Input High Current
CLK0, CLK1, OE, CLK_
SEL, CLK_EN
V
DD
= V
IN
= 2.625V 5 µA
I
IL
Input Low Current
CLK0, CLK1, OE, CLK_
SEL, CLK_EN
V
DD
= 32.625V,
V
IN
= 0V
-150 µA
V
OH
Output High Voltage; NOTE 1 1.8 V
V
OL
Output Low Voltage; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information Section, 2.5V Output Load Test
Circuit Diagram.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 3.6 V
V
IL
Input Low Voltage 0.8 V
I
IN
Input Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
-100 µA
V
OH
Output High Voltage; NOTE 1 I
OH
= -20mA 2.5 V
V
OL
Output Low Voltage; NOTE 1 I
OL
= 20mA 0.4 V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. See Parameter Measurement Information Section, 3.3V Output Load Test
Circuit Diagram.
P1-P3P4-P6P7-P9P10-P12

83947AYI-147LF

Mfr. #:
Buy 83947AYI-147LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 9 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
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