83947AYI-147LF

83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20164
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
PD
Propagation Delay, NOTE 1
f 250MHZ
2 4.2 ns
tsk(o) Output Skew; NOTE 2, 5
Measured on
rising edge @V
DDO
/2
115 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
Measured on
rising edge @V
DDO
/2
500 ps
tjit(Ø)
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
(12KHz to 20MHz)
0.2
ps
t
R
/ t
F
Output Rise/Fall Time 0.8V to 2.0V 0.2 1 ns
t
PW
Output Pulse Width f > 133MHz t
Period
/2 - 1 t
Period
/2 + 1 ns
odc Output Duty Cycle
f 133MHz
40 60 %
t
EN
Output Enable Time; NOTE 4 10 ns
t
DIS
Output Disable Time; NOTE 4 10 ns
t
S
Clock Enable Setup Time 0 ns
t
S
Clock Enable Hold Time 1 ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, V
DD
= V
DDO
= 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
t
PD
Propagation Delay, NOTE 1
f 250MHZ
2.4 4.5 ns
tsk(o) Output Skew; NOTE 2, 5
Measured on
rising edge @V
DDO
/2
130 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
Measured on
rising edge @V
DDO
/2
600 ps
tjit(Ø)
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
(12KHz to 20MHz) 0.1 ps
t
R
/ t
F
Output Rise/Fall Time 20% - 80% 300 800 ps
t
PW
Output Pulse Width t
Period
/2 - 1.2 t
Period
/2 + 1.2 ns
t
EN
Output Enable Time; NOTE 4 10 ns
t
DIS
Output Disable Time; NOTE 4 10 ns
t
S
Clock Enable Setup Time 0 ns
t
S
Clock Enable Hold Time 1 ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20165
ADDITIVE PHASE JITTER
The spectral purity in a band at a specifi c offset from the fun-
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specifi ed plot in many
applications. Phase noise is defi ned as the ratio of the noise
power present in a 1Hz band at a specifi ed offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in the
As with most timing specifi cations, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise fl oor of the equipment is higher
than the noise fl oor of the device. This is illustrated above. The
1Hz band to the power in the fundamental. When the required
offset is specifi ed, the phase noise is called a dBc value, which
simply means dBm at a specifi ed offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device meets the noise fl oor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20166
PARAMETER MEASUREMENT INFORMATION
2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT SKEW
3.3V OUTPUT RISE/FALL TIME
2.5V OUTPUT RISE/FALL TIME

83947AYI-147LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 9 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
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