83947I-147 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 18, 20167
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of 83947I-147 application sche-
matic. In this example, the device is operated at V
CC
=3.3V. The
decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVCMOS driver.
C4
0.1u
VCC
Zo = 50 Ohm
R3 43
R2 43
R1 43
C2
0.1u
(U1-22)
C3
0.1u
C1
0.1u
C3
0.1u
(U1-10)
VDDO
(U1-18)
C5
0.1u
VDDO
(U1-14)
Zo = 50
U1
ICS83947I-147
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
GND
VDDO
Q8
GND
Q7
VDDO
Q6
GND
GND
VDDO
Q5
GND
Q4
VDDO
Q3
GND
GND
VDDO
Q0
GND
Q1
VDDO
Q2
GND
VCC
VDD=3.3V
LVCMOS
Zo = 50
Zo = 50 Ohm
(U1-27)
VDD
V DDO=3. 3V
LVCMOS
C2
0.1u
(U1-31)
R3 43
For the LVCMOS output drivers, only one termination example
is shown in this schematic. Additional termination approaches
are shown in the LVCMOS Termination Application Note (refer
to ICS website).
FIGURE 1. 83947I-147 SCHEMATIC LAYOUT
