HCPL-0723-060E

10
6.5
7.0
7.5
8.0
8.5
9.0
-40 -20 0 20 40 60 80 100
I
DD1L
- LOGIC LOW INPUT SUPPLY
T
A
(°C)
0.4
0.45
0.5
0.55
0.6
-40 -20 0 20 40 60 80 100
T
A
(°C)
I
DD1H
- LOGIC HIGH INPUT SUPPLY
1.0
1.5
2.0
2.5
3.0
-40 -20 0 20 40 60 80 100
I
DD2L
- LOGIC LOW OUTPUT SUPPLY
T
A
(°C)
1
1.5
2
2.5
3
-40 -20 0 20 40 60 80 100
T
A
(°C)
I
DD2H
- LOGIC HIGH OUTPUT SUPPLY
CURRENT (mA)
CURRENT (mA) CURRENT (mA)
CURRENT (mA)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 -20 0 20 40 60 80 100
PWD (ns)
T
A
(°C)
T
plh
T
phl
-40
-20
0 20 40 60 80 100
10
12
14
16
18
20
22
T
phl
, T
plh
(ns)
T
A
(°C)
Figure 1: Typical Logic Low Input Supply Current vs. temperature Figure 2. Typical Logic High Input Supply Current vs. temperature
Figure 3. Typical Logic Low Output Supply Current vs. temperature Figure 4. Typical Logic High Output Supply Current vs. temperature
Figure 5. Typical propagation delay vs. temperature Figure 6. Typical pulse width distortion vs. temperature
11
Application Information
Bypassing and PC Board Layout
The HCPL-7723/0723 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-7723/0723 use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 8 illustrates the recommended
printed circuit board layout for the HCPL-7723/0723.
Figure 9. Timing diagram to illustrate propagation delay, tplh and tphl.
INPUT
t
PLH
t
PHL
OUTPUT
V
I
V
O
10%
90%90%
10%
V
OH
V
OL
0 V
50%
5 V CMOS
2.5 V CMOS
Figure 7. Functional diagram.
Figure 8. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation Delay is a gure of merit which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 9. The propagation delay from low
to high (t
PLH
) is the amount of time required for an input
signal to propagate to the output, causing the output to
change from low to high. Similarly, the propagation delay
from high to low (t
PHL
) is the amount of time required for
the input signal to propagate to the output, causing the
output to change from high to low.
7
5
6
8
2
3
4
1
GND
2
C1 C2
NC
V
DD2
NC
V
O
V
DD1
V
I
720
YWW
C1, C2 = 0.01 µF TO 0.1 µF
GND
1
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0566EN
AV02-0643EN - February 26, 2013
Pulse-width distortion (PWD) is the dierence between
t
PHL
and t
PLH
and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse width
is tolerable.
Propagation delay skew, t
PSK
, is an important parameter
to consider in parallel data applica tions where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, dierences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
dierent times. If this dierence in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocou-
plers.
Propagation delay skew is dened as the dierence
between the minimum and maximum propagation
delays, either t
PLH
or t
PHL
, for any given group of opto-
couplers which are operating under the same conditions
(i.e., the same drive current, supply voltage, output load,
and operating temperature). As illustrated in Figure 10,
if the inputs of a group of optocouplers are switched
either ON or OFF at the same time, t
PSK
is the dierence
between the shortest propagation delay, either t
PLH
or
t
PHL
, and the longest propagation delay, either t
PLH
or
t
PHL
.
Figure 10. Timing diagram to illustrate propagation delay skew, tpsk.
50%
50%
t
PSK
V
I
V
O
V
I
V
O
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
t
PSK
Figure 11. Parallel data transmission example.
As mentioned earlier, t
PSK
can determine the maximum
parallel data transmission rate. Figure 11 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The gure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked o of the rising edge of
the clock.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure 11 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consid-
erations, the absolute minimum pulse width that can
be sent through optocouplers in a parallel application is
twice t
PSK
. A cautious design should use a slightly longer
pulse width to ensure that any additional uncertainty in
the rest of the circuit does not cause a problem.
The HCPL-7723/0723 optocouplers oer the advantage of
guaranteed specications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.

HCPL-0723-060E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 50MBd 1Ch 150mA
Lifecycle:
New from this manufacturer.
Delivery:
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