HCPL-0723-060E

7
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature T
S
–55 125 °C
Ambient Operating Temperature
[1]
T
A
–40 85 °C
Supply Voltages V
DD1
, V
DD2
0 6.0 Volts
Input Voltage V
I
–0.5 V
DD1
+0.5 Volts
Output Voltage V
O
–0.5 V
DD2
+0.5 Volts
Average Output Current I
O
10 mA
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reow Temperature Prole See Solder Reow Temperature Prole Section
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Ambient Operating Temperature T
A
–40 85 °C
Supply Voltages V
DD1
, V
DD2
4.5 5.5 V
Logic High Input Voltage V
IH
2.0 V
DD1
V
Logic Low Input Voltage V
IL
0.0 0.8 V
Input Signal Rise and Fall Times t
r,
t
f
1.0 ms
Electrical Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
= +25°C, V
DD1
= V
DD2
= +5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Logic Low Input Supply Current
[2]
I
DD1L
8.4 10 mA V
I
= 0 V; Figure 1
Logic High Input Supply Current
[2]
I
DD1H
0.6 3 mA V
I
= V
DD1
; Figure 2
Output Supply Current I
DD2L
2.1 5 mA Figure 3
I
DD2H
2.0 5 mA Figure 4
Input Current I
I
–10 10 µA
Logic High Output Voltage V
OH
4.4 5.0 V I
O
= –20 µA, V
I
= V
IH
4.0 4.8 V I
O
= –4 mA, V
I
= V
IH
Logic Low Output Voltage V
OL
0 0.1 V I
O
= 20 µA, V
I
= V
IL
0.5 1.0 V I
O
= 4 mA, V
I
= V
IL
8
Switching Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
= +25°C, V
DD1
= V
DD2
= +5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Propagation Delay Time to Logic t
PHL
16 22 ns C
L
= 15 pF CMOS Signal Levels; Figure 5
Low Output
[3]
Propagation Delay Time to Logic t
PLH
16 22 ns C
L
= 15 pF CMOS Signal Levels; Figure 5
High Output
[3]
Pulse Width PW 20 ns C
L
= 15 pF CMOS Signal Levels
Maximum Data Rate 50 MBd C
L
= 15 pF CMOS Signal Levels
Pulse Width Distortion
[4]
|t
PHL
- t
PLH
| |PWD| 1 2 ns C
L
= 15 pF CMOS Signal Levels; Figure 6
Propagation Delay Skew
[5]
t
PSK
16 ns C
L
= 15 pF CMOS Signal Levels
Output Rise Time (10% – 90%) t
R
8 ns C
L
= 15 pF CMOS Signal Levels
Output Fall Time (90% - 10%) t
F
6 ns C
L
= 15 pF CMOS Signal Levels
Common Mode Transient Immunity |CM
H
|
10 15 kV/µs V
CM
= 1000 V
,
T
A
= 25°C,
at Logic High Output
[6]
V
I
= V
DD1,
V
O
> 0.8 V
DD2
Common Mode Transient Immunity |CM
L
|
10 15 kV/µs V
CM
= 1000 V
,
T
A
= 25°C,
at Logic Low Output
[6]
V
I
= 0 V
,
V
O
< 0.8 V
9
Package Characteristics
All Typical Specications are at T
A
= 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Input-Output Momentary –7723 V
ISO
3750 V rms RH ≤ 50%, t = 1 min,
Withstand Voltage
[7,8,9]
Option 020 5000 T
A
= 25°C
–0723 3750
Input-Output Resistance
[7]
R
I-O
10
12
V
I-O
= 500 V dc
Input-Output Capacitance C
I-O
0.6 pF f = 1 MHz
Input Capacitance
[10]
C
I
3.0 pF
Input IC Junction-to-Case –7723 θ
jci
145 °C/W Thermocouple located at
Thermal Resistance –0723 160 center underside of package
Output IC Junction-to-Case –7723 θ
jco
145 °C/W
Thermal Resistance –0723 135
Package Power Dissipation P
PD
150 mW
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when V
I
is low and OFF when V
I
is high.
3. t
PHL
propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the V
O
sig-
nal. t
PLH
propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the V
O
signal.
4. PWD is dened as |t
PHL
- t
PLH
|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
5. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at any given temperature
within the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CML is the maximum com-
mon mode voltage slew rate that can be sustained while maintaining V
O
< 0.8 V. The common mode voltage slew rates apply to both rising
and falling common mode voltage edges.
7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detec-
tion current limit, I
I-O
≤ 5 µA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detec-
tion current limit. I
I-O
≤ 5 µA.)
9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specication or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.
10. C
I
is the capacitance measured at pin 2 (V
I
).

HCPL-0723-060E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 50MBd 1Ch 150mA
Lifecycle:
New from this manufacturer.
Delivery:
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