MAX1279BETC+ Datasheet MAX1279BETC+, MAX1277BCTC+T, MAX1279ACTC+T | P10-P12

MAX1277/MAX1279

True-Differential Analog Input T/H

The equivalent circuit of Figure 4 shows the input archi-

tecture of the MAX1277/MAX1279, which is composed

of a T/H, a comparator, and a switched-capacitor digi-

tal-to-analog converter (DAC). The T/H enters its track-

ing mode on the 14th SCLK rising edge of the previous

conversion. Upon power-up, the T/H enters its tracking

mode immediately. The positive input capacitor is con-

nected to AIN+. The negative input capacitor is con-

nected to AIN-. The T/H enters its hold mode on the

falling edge of CNVST and the difference between the

sampled positive and negative input voltages is convert-

ed. The time required for the T/H to acquire an input sig-

nal is determined by how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens. The acquisition time,

ACQ

, is the minimum time needed for the signal to be

acquired. It is calculated by the following equation:

ACQ

≥ 9 × (RS + R

) × 16pF

where R

= 200Ω, and RS is the source impedance of

the input signal.

Note: t

ACQ

is never less than 125ns and any source

impedance below 12Ω does not significantly affect the

ADC’s AC performance.

Input Bandwidth

The ADC’s input-tracking circuitry has a 15MHz small-

signal bandwidth, making it possible to digitize high-

speed transient events and measure periodic

signals with bandwidths exceeding the ADC’s sampling

rate by using undersampling techniques. To avoid

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes that clamp the analog input

to V

and GND allow the analog input pins to swing

from GND - 0.3V to V

+ 0.3V without damage. Both

inputs must not exceed V

or be lower than GND for

accurate conversions.

Serial Interface

Initialization After Power-Up

and Starting a Conversion

Upon initial power-up, the MAX1277/MAX1279 require a

complete conversion cycle to initialize the internal cali-

bration. Following this initial conversion, the part is ready

for normal operation. This initialization is only required

after a hardware power-up sequence and is not required

after exiting partial or full power-down mode.

To start a conversion, pull CNVST low. At CNVST’s

falling edge, the T/H enters its hold mode and a conver-

sion is initiated. SCLK runs the conversion and the data

can then be shifted out serially on DOUT.

1.5Msps, Single-Supply, Low-Power, True-

Differential, 12-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

DOUT

MODE

SCLK

CNVST

DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH

CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE

ONE 8-BIT TRANSFER

1ST SCLK RISING EDGE

PPD

0 0 0 D11 D10 D9 D8 D7

NORMAL

REF

ENABLED (2.048V)

Figure 6. SPI Interface—Partial Power-Down Mode

Figure 5. Interface-Timing Sequence

ACQUIRE

CONTINUOUS-CONVERSION

SELECTION WINDOW

CNVST

SETUP

DOUT

SCLK

41412 83 16

HIGH IMPEDANCE

D1D4D6 D5D9 D8 D7D11 D10

POWER-MODE SELECTION WINDOW

D0D2D3

Timing and Control

Conversion-start and data-read operations are con-

trolled by the CNVST and SCLK digital inputs. Figures 1

and 5 show timing diagrams, which outline the serial-

interface operation.

A CNVST falling edge initiates a conversion sequence;

the T/H stage holds the input voltage, the ADC begins

to convert, and DOUT changes from high impedance to

logic low. SCLK is used to drive the conversion

process, and it shifts data out as each bit of the conver-

sion is determined.

SCLK begins shifting out the data after the 4th rising

edge of SCLK. DOUT transitions t

DOUT

after each

SCLK’s rising edge and remains valid 4ns (t

DHOLD

)

after the next rising edge. The 4th rising clock edge

produces the MSB of the conversion at DOUT, and the

MSB remains valid 4ns after the 5th rising edge. Since

there are 12 data bits and 3 leading zeros, at least 16

rising clock edges are needed to shift out these bits.

For continuous operation, pull CNVST high between the

14th and the 16th SCLK rising edges. If CNVST stays

low after the falling edge of the 16th SCLK cycle, the

DOUT line goes to a high-impedance state on either

CNVST’s rising edge or the next SCLK’s rising edge.

Partial Power-Down and

Full Power-Down Modes

Power consumption can be reduced significantly by plac-

ing the MAX1277/MAX1279 in either partial power-down

mode or full power-down mode. Partial power-down

mode is ideal for infrequent data sampling and fast wake-

up time applications. Pull CNVST high after the 3rd SCLK

rising edge and before the 14th SCLK rising edge to

enter and stay in partial power-down mode (see Figure

6). This reduces the supply current to 2mA. While in par-

tial power-down mode, the reference remains enabled to

allow valid conversions once the IC is returned to normal

mode. Drive CNVST low and allow at least 14 SCLK

cycles to elapse before driving CNVST high to exit partial

power-down mode.

Full power-down mode is ideal for infrequent data sam-

pling and very low supply current applications. The

MAX1277/MAX1279 have to be in partial power-down

mode to enter full power-down mode. Perform the

SCLK/CNVST sequence described above to enter par-

tial power-down mode. Then repeat the same

sequence to enter full power-down mode (see Figure

7). Drive CNVST low, and allow at least 14 SCLK cycles

to elapse before driving CNVST high to exit full power-

down mode. While in full power-down mode, the refer-

ence is disabled to minimize power consumption. Be

sure to allow at least 2ms recovery time after exiting full

power-down mode for the reference to settle. In

partial/full power-down mode, maintain a logic low or a

logic high on SCLK to minimize power consumption.

Transfer Function

Figure 8 shows the unipolar transfer function for the

MAX1277. Figure 9 shows the bipolar transfer function for

the MAX1279. The MAX1277 output is straight binary,

while the MAX1279 output is two’s complement.

Applications Information

Internal Reference

The MAX1277/MAX1279 have an on-chip voltage refer-

ence trimmed to 2.048V. The internal reference output

is connected to REF and also drives the internal capac-

itive DAC. The output can be used as a reference volt-

age source for other components and can source up to

2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF

capacitor to RGND.

The internal reference is continuously powered up dur-

ing both normal and partial power-down modes. In full

power-down mode, the internal reference is disabled.

Be sure to allow at least 2ms recovery time after hard-

ware power-up or exiting full power-down mode for the

reference to reach its intended value.

MAX1277/MAX1279

1.5Msps, Single-Supply, Low-Power, True-

Differential, 12-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

Figure 7. SPI Interface—Full Power-Down Mode

1ST SCLK RISING EDGE 1ST SCLK RISING EDGE

0 0 0 D11 D10 D9 D8 D7

DOUT

MODE

SCLK

CNVST

000000

FPDRECOVERYPPDNORMAL

DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH

EXECUTE PARTIAL POWER-DOWN TWICE

FIRST 8-BIT TRANSFER

SECOND 8-BIT TRANSFER

REF

ENABLED (2.048V)

DISABLED

MAX1277/MAX1279

How to Start a Conversion

An analog-to-digital conversion is initiated by CNVST,

clocked by SCLK, and the resulting data is clocked out on

DOUT by SCLK. With SCLK idling high or low, a falling

edge on CNVST begins a conversion. This causes the

analog input stage to transition from track to hold mode,

and for DOUT to transition from high impedance to being

actively driven low. A total of 16 SCLK cycles are required

to complete a normal conversion. If CNVST is low during

the 16th falling SCLK edge, DOUT returns to high imped-

ance on the next rising edge of CNVST or SCLK, enabling

the serial interface to be shared by multiple devices. If

CNVST returns high after the 14th, but before the 16th

SCLK rising edge, DOUT remains active so continuous

conversions can be sustained. The highest throughput is

achieved when performing continuous conversions. Figure

10 illustrates a conversion using a typical serial interface.

Connection to

Standard Interfaces

The MAX1277/MAX1279 serial interface is fully compati-

ble with SPI/QSPI and MICROWIRE (see Figure 11). If a

serial interface is available, set the CPU’s serial interface

in master mode so the CPU generates the serial clock.

Choose a clock frequency up to 24MHz.

SPI and MICROWIRE

When using SPI or MICROWIRE, the MAX1277/ MAX1279

are compatible with all four modes programmed with the

CPHA and CPOL bits in the SPI or MICROWIRE control

DOUT goes low, indicating a conversion is in progress.

Two consecutive 1-byte reads are required to get the full

12 bits from the ADC. DOUT transitions on SCLK rising

edges. DOUT is guaranteed to be valid t

DOUT

later and

remains valid until t

DHOLD

after the following SCLK rising

edge. When using CPOL = 0 and CPHA = 0, or CPOL = 1

and CPHA = 1, the data is clocked into the µP on the fol-

lowing rising edge. When using CPOL = 0 and CPHA = 1,

or CPOL = 1 and CPHA = 0, the data is clocked into the

µP on the next falling edge. See Figure 11 for connections

and Figures 12 and 13 for timing. See the

Timing

Characteristics

section to determine the best mode to use.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 12 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1277/MAX1279 require 16 clock cycles

from the µP to clock out the 12 bits of data. Figure 14

shows a transfer using CPOL = 1 and CPHA = 1. The

conversion result contains three zeros, followed by the

12 data bits, and a trailing zero with the data in MSB-

1.5Msps, Single-Supply, Low-Power, True-

Differential, 12-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

OUTPUT CODE

FULL-SCALE

TRANSITION

111...111

12 3

FS - 3/2 LSB

FS = V

REF

DIFFERENTIAL INPUT

VOLTAGE (LSB)

1 LSB =

REF

4096

111...110

111...101

000...011

000...010

000...001

000...000

ZS = 0

Figure 8. Unipolar Transfer Function (MAX1277 Only)

OUTPUT CODE

FULL-SCALE

TRANSITION

FS0-FS

FS - 3/2 LSB

DIFFERENTIAL INPUT

VOLTAGE (LSB)

011...111

011...110

000...010

000...001

000...000

111...111

111...110

111...101

100...001

100...000

1 LSB =

REF

4096

FS =

REF

- FS =

-V

REF

ZS = 0

Figure 9. Bipolar Transfer Function (MAX1279 Only)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX1279BETC+

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Analog to Digital Converters - ADC 12-Bit 1.5Msps 3.6V Precision ADC

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