MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
4 _______________________________________________________________________________________
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for V
L
> 2.7V. See the
Typical Operating Characteristics
section for recommended sampling
speeds for V
L
< 2.7V.
Note 8: Digital supply current is measured with the V
IH
level equal to V
L
, and the V
IL
level equal to GND.
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, V
L
= V
DD
, f
SCLK
= 24MHz, 50% duty cycle, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are
at T
A
= +25°C.)
