MAX1277/MAX1279
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the V
L
pin to the ADSP21_ _ _ supply voltage
when the MAX1277/MAX1279 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the V
DD
power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1277/MAX1279 are mea-
sured using the end-points method.
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
16 ______________________________________________________________________________________
MAX1277
MAX1279
ADSP21_ _ _
V
L
SCLK
CNVST
DOUT
VDDINT
RCLK
RFS
TCLK
TFS
DR
Figure 19. Interfacing to the ADSP21_ _ _
10μF
0.1μF
10μF
0.1μF
GND V
L
SUPPLIES
DGND V
L
DIGITAL
CIRCUITRY
V
DD GND RGND
V
L
MAX1277
MAX1279
Figure 20. Power-Supply Grounding Condition
0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
DOUT
SCLK
CNVST
0 0
1
1
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t
AD
) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analog-to-
digital noise is caused by quantization error, and results
directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (Signal
RMS
/ Noise
RMS
)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza-
tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through V
5
are the amplitudes of the 2nd- through 5th-
order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the
input signal amplitude attenuates by 3dB for a full-scale
input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the sig-
nal to noise plus distortion (SINAD) is equal to 68dB.
Intermodulation Distortion (IMD)
Any device with nonlinearities creates distortion prod-
ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency rela-
tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.
The intermodulation products are as follows:
2nd-order intermodulation products (IM2): f
1
+ f
2
,
f
2
- f
1
3rd-order intermodulation products (IM3): 2f
1
- f
2
,
2f
2
- f
1
, 2f
1
+ f
2
, 2f
2
+ f
1
4th-order intermodulation products (IM4): 3f
1
- f
2
,
3f
2
- f
1
, 3f
1
+ f
2
, 3f
2
+ f
1
5th-order intermodulation products (IM5): 3f
1
- 2f
2
,
3f
2
- 2f
1
, 3f
1
+ 2f
2
, 3f
2
+ 2f
1
THD x
VVVV
V
log=
+++
20
2
2
3
2
4
2
5
2
1
ENOB
SINAD
( .)
.
=
176
602
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
______________________________________________________________________________________ 17
Chip Information
TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
12 TQFN T1244+3
21-0139
MAX1277/MAX1279
1.5Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0 8/04 Initial release
1 4/09 Removed commercial temperature grade parts from data sheet 1–8

MAX1279BETC+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 1.5Msps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
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