MAX5158/MAX5159
remains active. Data in the input registers is saved,
allowing the MAX5158/MAX5159 to recall the output
state prior to entering shutdown when returning to nor-
mal mode. Exit shutdown by recalling the previous con-
dition or by updating the DAC with new information.
When returning to normal operation (exiting shutdown),
wait 20µs for output stabilization.
Serial Interface
The MAX5158/MAX5159 3-wire serial interface is com-
patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits, 10
bits of data (MSB to LSB), and 3 sub-bits as shown in
Figure 4. The address and control bits determine the
MAX5158/MAX5159’s response, as outlined in Table 1.
Low-Power, Dual, 10-Bit Voltage-Output DACs
with Serial Interface
10 ______________________________________________________________________________________
FUNCTION
A0 C1 C0
D9..........................D0
(MSB) (LSB)
0 0 1 10-bit DAC data Load input register A; DAC registers are unchanged.
0 1 1 10-bit DAC data
Load all DAC registers from the shift register
(start up both DACs with new data.).
1 1 0 10-bit DAC data Load input register B; all DAC registers are updated.
0 1 0 10-bit DAC data Load input register A; all DAC registers are updated.
1 0 1 10-bit DAC data Load input register B; DAC registers are unchanged.
0 0 0 1 1 0 x xxxxxx
Shut down DAC A (provided PDL = 1).
0 0 0 1 0 1 x xxxxxx
Update DAC register B from input register B
(start up DAC B with data previously stored in input register B).
0 0 0 0 0 1 x xxxxxx
Update DAC register A from input register A
(start up DAC A with data previously stored in input register A).
1 1 1 xxxxxxxxxx
Shut down both DACs (provided PDL = 1).
1 0 0 xxxxxxxxxx
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
0 0 0 1 1 1 x xxxxxx
Shut down DAC B (provided PDL = 1).
0 0 0 0 1 0 x xxxxxx UPO goes low (default).
0 0 0 0 1 1 x xxxxxx UPO goes high.
0 0 0 1 0 0 1 xxxxxx Mode 1, DOUT clocked out on SCLK’s rising edge.
0 0 0 1 0 0 0 xxxxxx Mode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 0 0 0 0 x xxxxxx No operation (NOP).
Table 1. Serial-Interface Programming Command
x = Don’t care
Note: When A0, C1, and C0 = 0, then D9, D8, D7, and D6 become control bits. S2–S0 are sub bits, always zero.
SCLK
DIN
CS
SK
SO
I/O
MAX5158
MAX5159
MICROWIRE
PORT
Figure 2. Connections for Microwire
16-BIT SERIAL WORD
S2–S0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
The MAX5158/MAX5159’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated and the state of the registers
when exiting shutdown. The 3-bit address/control deter-
mines the following:
registers to be updated
clock edge on which data is to be clocked out via
the serial-data output (DOUT)
state of the user-programmable logic output
configuration of the device after shutdown.
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
MAX5158/MAX5159
Low-Power, Dual, 10-Bit, Voltage-Output DACs
with Serial Interface
DIN
SCLK
CS
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
+5V
CPOL = 0, CPHA = 0
MAX5158
MAX5159
Figure 3. Connections for SPI/QSPI
Figure 5. Serial-Interface Timing Diagram
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
A0 S0
C0
D9
D8
D7
D6 D3 D2 D1 D0 S2 S1D5 D4
______________________________________________________________________________________ 11
Figure 4. Serial-Data Format
MSB..................................................................................LSB
16 Bits of Serial Data
Address Bits Control Bits MSB....DataBits...LSB Sub Bits
A0 C1, C0
D9.................. ......D0
S2–S0
1 Address/
2 Control Bits
10 Data Bits
000
MAX5158/MAX5159
Low-Power, Dual, 10-Bit Voltage-Output DACs
with Serial Interface
12 ______________________________________________________________________________________
SCLK
DIN
t
CSO
t
CSS
t
CL
t
CH
t
CP
t
CSW
t
CS1
t
CSH
t
DS
t
DH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
TO OTHER
SERIAL DEVICES
MAX5158
MAX5159
DIN
SCLK
CS
MAX5158
MAX5159
MAX5158
MAX5159
DINDOUT DOUT DOUT
SCLK
CS
DIN
SCLK
CS
TO OTHER
SERIAL DEVICES
MAX5158
MAX5159
DIN
SCLK
CS
MAX5158
MAX5159
DIN
SCLK
CS
MAX5158
MAX5159
DIN
SCLK
CS
DIN
SCLK
CS1
CS2
CS3
Figure 7. Daisy Chaining MAX5158/MAX5159s
Figure 8. Multiple MAX5158/MAX5159s Sharing a Common DIN Line

MAX5158CPE

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union