MAX5158CPE Datasheet MAX5158CPE, MAX5158CEE, MAX5159EPE | P13-P15

Serial-Data Output

The serial-data output, DOUT, is the internal shift regis-

ter’s output. DOUT allows for daisy chaining of devices

and data readback. The MAX5158/MAX5159 can be

programmed to shift data out of DOUT on SCLK’s

falling edge (Mode 0) or on the rising edge (Mode 1).

Mode 0 provides a lag of 16 clock cycles, which main-

tains compatibility with SPI/QSPI and Microwire inter-

faces. In Mode 1, the output data lags 15.5 clock

cycles. On power-up, the device defaults to Mode 0.

User-Programmable Logic Output (UPO)

UPO allows an external device to be controlled through

the serial interface (Table 1), thereby reducing the num-

ber of microcontroller I/O pins required. On power-up,

UPO is low.

Power-Down Lockout Input (

PPDDLL

)

The power-down lockout pin (PDL) disables software

shutdown when low. When in shutdown, transitioning

PDL from high to low wakes up the part with the output

set to the state prior to shutdown. PDL can also be

used to asynchronously wake up the device.

Daisy Chaining Devices

Any number of MAX5158/MAX5159s can be daisy

chained by connecting the DOUT pin of one device to

the DIN pin of the following device in the chain (Figure 7).

Since the MAX5158/MAX5159’s DOUT pin has an internal

active pull-up, the DOUT sink/source capability deter-

mines the time required to discharge/charge a capacitive

load. Refer to the digital output V

and V

specifica-

tions in the

Electrical Characteristics

Figure 8 shows an alternate method of connecting sev-

eral MAX5158/MAX5159s. In this configuration, the

data bus is common to all devices; data is not shifted

through a daisy chain. More I/O lines are required in

this configuration because a dedicated chip-select

input (CS) is required for each IC.

__________Applications Information

Unipolar Output

Figure 9 shows the MAX5158/MAX5159 configured for

unipolar, rail-to-rail operation with a gain of +2V/V. The

MAX5158 can produce a 0V to 4.096V output with a

2.048V reference (Figure 9), while the MAX5159 can

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

Table 2. Unipolar Code Table (Gain = +2)

MAX5158

MAX5159

DAC_

GAIN = +2V/V

REF_

OUT_

OS_

DGNDAGND

+5V/+3V

Figure 9. Unipolar Output Circuit (Rail-to-Rail)

MAX5158

MAX5159

DAC _

AGND DGND

REF_

OUT_

OS_

+5V/+3V

______________________________________________________________________________________ 13

ANALOG OUTPUT

11 1111 1111 (000)

10 0000 0001 (000)

DAC CONTENTS

MSB LSB

10 0000 0000 (000)

01 1111 1111 (000)

00 0000 0000 (000) 0V

00 0000 0001 (000)

1023

1024

x 2

REF













513

1024

x 2

REF













512

1024

x 2 V

REF REF













511

1024

x 2

REF













1024

REF













Figure 10. Setting OS_ for Output Offset

Note: ( ) are for the sub bits.

MAX5158/MAX5159

produce a range of 0V to 2.5V with a 1.25V reference.

Table 2 lists the unipolar output codes. An offset to the

output can be achieved by connecting a voltage to

OS_, as shown in Figure 10. By applying V

_ = -1V,

the output values will range between 1V and (1V +

REF

x 2).

Bipolar Output

The MAX5158/MAX5159 can be configured for a bipo-

lar output, as shown in Figure 11. The output voltage is

given by the equation (OS_ = AGND):

OUT

= V

REF

[((2 x NB) / 1024) - 1]

where NB represents the numeric value of the DAC’s

binary input code. Table 3 shows digital codes and the

corresponding output voltage for Figure 11’s circuit.

Using an AC Reference

In applications where the reference has an AC signal

component, the MAX5158/MAX5159 have multiplying

capabilities within the reference input voltage range

specifications. Figure 12 shows a technique for apply-

ing a sinusoidal input to REF_, where the AC signal is

offset before being applied to the reference input.

Harmonic Distortion and Noise

The total harmonic distortion plus noise (THD+N) is typ-

ically less than -78dB at full scale with a 1Vp-p input

swing at 5kHz. The typical -3dB frequency is 300kHz

for both devices, as shown in the

Typical Operating

Characteristics.

Low-Power, Dual, 10-Bit Voltage-Output DACs

with Serial Interface

14 ______________________________________________________________________________________

Table 3. Bipolar Code Table

ANALOG OUTPUT

11 1111 1111 (000)

10 0000 0001 (000)

DAC CONTENTS

MSB LSB

10 0000 0000 (000) 0V

01 1111 1111 (000)

00 0000 0000 (000)

00 0000 0001 (000)

511

512

REF













512

REF













-V

512

REF













-V

511

512

REF













-V

512

- V

REF REF













AGNDDGND

MAX5158

MAX5159

DAC _

REF_

OS_

OUT_

10k 10k

10k

V-

V+

OUT

+5V/+3V

Figure 11. Bipolar Output Circuit

DAC_

OUT_

MAX5158

MAX5159

10k

26k

OS_

REF

DGNDAGND

+5V/

+3V

REFERENCE

INPUT

500mVp-p

MAX495

+5V/+3V

Figure 12. AC Reference Input Circuit

AGND

DIN

µP

DGND

MAX5158

MAX5159

DAC _

REF_

OS_

OUT_

V-

V+

PHOTODIODE

V+

OUT

PULLDOWN

+5V/+3V

Figure 13. Digital Calibration

Note: ( ) are for the sub bits.

Digital Calibration and

Threshold Selection

Figure 13 shows the MAX5158/MAX5159 in a digital

calibration application. With a bright light value applied

to the photodiode (on), the DAC is digitally ramped until

it trips the comparator. The microprocessor (µP) stores

this “high” calibration value. Repeat the process with a

dim light (off) to obtain the dark current calibration. The

µP then programs the DAC to set an output voltage at

the midpoint of the two calibrated values. Applications

include tachometers, motion sensing, automatic read-

ers, and liquid clarity analysis.

Digital Control of Gain and Offset

The two DACs can be used to control the offset and

gain for curve-fitting nonlinear functions, such as trans-

ducer linearization or analog compression/expansion

applications. The input signal is used as the reference

for the gain-adjust DAC, whose output is summed with

the output from the offset-adjust DAC. The relative

weight of each DAC output is adjusted by R1, R2, R3,

and R4 (Figure 14).

Power-Supply Considerations

On power-up, the input and DAC registers clear (set to

zero code). For rated performance, V

REF_

should be at

least 1.4V below V

. Bypass the power supply with a

4.7µF capacitor in parallel with a 0.1µF capacitor

to AGND. Minimize lead lengths to reduce lead

inductance.

Grounding and Layout Considerations

Digital and AC transient signals on AGND can create

noise at the output. Connect AGND to the highest quality

ground available. Use proper grounding techniques,

such as a multilayer board with a low-inductance ground

plane. Carefully lay out the traces between channels to

reduce AC cross-coupling and crosstalk. Wire-wrapped

boards and sockets are not recommended. If noise

becomes an issue, shielding may be required.

MAX5158/MAX5159

Low-Power, Dual, 10-Bit, Voltage-Output DACs

with Serial Interface

______________________________________________________________________________________ 15

AGND DGND

MAX5158

MAX5159

DACA

REFA

REF

SCLK

DIN

REFB

OUTB

OSB

OUTA

OSA

OUT

DACB

INPUT

REG A

INPUT

REG B

DAC

REG A

DAC

REG B

– OFFSET

[ ]

OUT

GAIN

[ ]

2NA

1024

NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.

NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.

R1+R2

2NB

1024

(

)(

)

(

REF

)(

)

[ ] [ ]

SHIFT

Figure 14. Digital Control of Gain and Offset

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX5158CPE

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Digital to Analog Converters - DAC Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface

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MAX5158CPE

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