RMLV1616A Series
R10DS0258EJ0100 Rev.1.00 Page 10 of 14
2016.01.06
Write Cycle (2)
*28
(WE# CLOCK, OE# Low Fixed)
Note 28. BYTE# pin supported by only 48pin TSOP (I) and 52pin µTSOP (II) types.
BYTE# ≥ Vcc - 0.2V (Word mode) or BYTE# ≤ 0.2V (Byte mode)
29. t
WP
is the interval between write start and write end.
A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active.
A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive.
30. t
WHZ
is defined as the time when the DQ pins enter a high-impedance state and are not referred to the DQ
levels.
31. This parameter is sampled and not 100% tested.
32. During this period, DQ pins are in the output state so input signals must not be applied to the DQ pins.
CS1#
t
CW
t
WHZ
OE#
WE#
t
DH
t
WC
LB#,UB#
t
BW
CS2
t
CW
Valid address
t
WR
t
AW
t
AS
t
WP
t
DW
t
OW
*29
*30,31
V
IL
OE# = “L” level
Valid Data
*32
*32
A
0~19
A
-1~19
(Word Mode)
(Byte Mode)
DQ
0~15
DQ
0~7
(Word Mode)
(Byte Mode)
