83023AMILFT Datasheet 83023AMILFT, 83023AMILF | P4-P6

83023I Data Sheet

TABLE 4. AC CHARACTERISTICS, V

= 3.3V±0.3V, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

MAX

Maximum Output Frequency 350 MHz

Propagation Delay; NOTE 1 1.8 2.1 2.4 ns

tsk(o) Output Skew; NOTE 2, 4 60 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 500 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

100MHz, Integration Range

(637kHz-10MHz)

0.14 ps

Output Rise Time 0.8V to 2V 100 250 400 ps

Output Fall Time 0.8V to 2V 100 250 400 ps

odc Output Duty Cycle

f ≤ 166MHz

45 50 55 %

f > 166MHz 43 50 57 %

All parameters measured at f

MAX

unless noted otherwise. See Parameter Measurement Information.

NOTE 1: Measured from the differential input crossing point to V

/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

/2. Input clocks are phase aligned.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at V

/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

83023I Data Sheet

ADDITIVE PHASE JITTER

Additive Phase Jitter @ 100MHz

(12kHz to 20MHz)

= 0.14ps typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k 10k 100k 1M 10M 100M

The spectral purity in a band at a speciﬁ c offset from the fun-

damental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using

a Phase noise plot and is most often the speciﬁ ed plot in many

applications. Phase noise is deﬁ ned as the ratio of the noise

power present in a 1Hz band at a speciﬁ ed offset from the fun-

damental frequency to the power value of the fundamental. This

ratio is expressed in decibels (dBm) or a ratio of the power in the

As with most timing speciﬁ cations, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise ﬂ oor of the equipment is higher

than the noise ﬂ oor of the device. This is illustrated above. The

1Hz band to the power in the fundamental. When the required

offset is speciﬁ ed, the phase noise is called a dBc value, which

simply means dBm at a speciﬁ ed offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

device meets the noise ﬂ oor of what is shown, but can actually

be lower. The phase noise is dependant on the input source and

measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

83023I Data Sheet

PARAMETER MEASUREMENT INFORMATION

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

OUTPUT SKEW

PART-TO-PART SKEW

3.3V OUTPUT LOAD AC TEST CIRCUIT

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

DIFFERENTIAL INPUT LEVEL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

83023AMILFT

Mfr. #:

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Manufacturer:

IDT

Description:

Clock Buffer Dual 1:1 Diff. to LV CMOS Translator/Buff

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83023AMILFT

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