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83023AMILFT

P1-P3P4-P6P7-P9P10-P12P13-P13
83023I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20157
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
INPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left fl oating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left fl oating. We recommend
that there is no trace attached.
83023I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20158
FIGURE 2C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
SWING
and V
OH
must
meet the V
PP
and V
CMR
input requirements. Figures 2A to 2E
show interface examples for the CLK/nCLK input driven by
the most common driver types. The input interfaces suggest-
FIGURE 2A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
ed here are examples only. Please consult with the vendor
of the driver component to confirm the driver termination
requirements. For example in Figure 2A, the input termination
applies for LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
83023I Data Sheet
©2015 Integrated Device Technology, Inc December 14, 20159
TRANSISTOR COUNT
The transistor count for 83023I is: 416
TABLE 5. θ
JA
VS. AIR FLOW TABLE FOR 8 LEAD SOIC
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
RELIABILITY INFORMATION
P1-P3P4-P6P7-P9P10-P12P13-P13

83023AMILFT

Mfr. #:
Buy 83023AMILFT
Manufacturer:
IDT
Description:
Clock Buffer Dual 1:1 Diff. to LV CMOS Translator/Buff
Lifecycle:
New from this manufacturer.
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