17
LTC1293/LTC1294/LTC1296
129346fs
Sharing the Serial Interface
The LTC1293/4/6 can share the same 3-wire serial inter-
face with other peripheral components or other LTC1293/
4/6’s (Figure 3). Now, the CS signals decide which LTC1293/
4/6 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1293/4/6 should be used with an analog ground
plane and single point grounding techniques. Do not use
wire wrapping techniques to breadboard and evaluate the
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
CLR P1.3 CLK GOES LOW
CLR A CLEAR ACC
RLC A ROTATE DATA BIT (B3) INTO ACC
MOV C,P1.2 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B2) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.2 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B1) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.2 READ DATA BIT INTO CARRY
SETB P1.4 CS GOES HIGH
RRC A ROTATE DATA BIT (B0) INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
MOV R3,A STORE LSBs IN R3
AJMP CONT START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
SETB P1.4 CS GOES HIGH
CONT MOV A,#87H DIN WORD FOR LTC1294
CLR P1.4 CS GOES LOW
MOV R4,#08H LOAD COUNTER
LOOP1 RLC A ROTATE DIN BIT INTO CARRY
CLR P1.3 CLK GOES LOW
MOV P1.2,C OUTPUT DIN BIT TO LTC1294
SETB P1.3 CLK GOES HIGH
DJNZ R4,LOOP1 NEXT DIN BIT
MOV P1,#04H P1.2 BECOMES AN INPUT
CLR P1.3 CLK GOES LOW
MOV R4,#09H LOAD COUNTER
LOOP MOV C,P1.2 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B3) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
DJNZ R4,LOOP NEXT DOUT BIT
MOV R2,A STORE MSBs IN R2
MOV C,P1.2 READ DATA BIT INTO CARRY
SETB P1.3 CLK GOES HIGH
LABEL MNEMONIC OPERAND COMMENTS
8051 CODE
8 CHANNELS 8 CHANNELS
8 CHANNELS
3
3
33
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1293/4/6s
2
10
OUTPUT PORT
SERIAL DATA
MPU
LTC1293 F03
LTC1294
CS
LTC1294
CS
LTC1294
CS
Figure 3. Several LTC1294 Sharing One 3-Wire Serial Interface
device. To achieve the optimum performance use a PC
board. The analog ground pin (AGND) should be tied
directly to the ground plane with minimum lead length (a
low profile socket is fine). The digital ground pin (DGND)
also can be tied directly to this ground pin because
minimal digital noise is generated within the chip itself.
V
CC
should be bypassed to the ground plane with a 22µF
(minimum value) tantalum with leads as short as possible
and as close as possible to the pin. A 0.1µF ceramic disk
also should be placed in parallel with the 22µF and again
with leads as short as possible and as close to V
CC
as
possible. AV
CC
and DV
CC
should be tied together on the
