7
LTC1293/LTC1294/LTC1296
129346fs
PI FU CTIO S
U
UU
# PIN FUNCTION DESCRIPTION
1 – 6 CH0 – CH5 Analog Inputs The analog inputs must be free of noise with respect to AGND.
7 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
8 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane.
9V
Negative Supply Tie V
to most negative potential in the circuit (Ground in single supply applications).
10 AGND Analog Ground AGND should be tied directly to the analog ground plane.
11 V
REF
Ref. Input The reference inputs must be kept free of noise with respect to AGND.
12 D
IN
Data Input The A/D configuration word is shifted into this input.
13 D
OUT
Digital Data Output The A/D conversion result is shifted out of this output.
14 CS Chip Select Input A logic low on this input enables data transfer.
15 CLK Clock This clock synchronizes the serial data transfer and controls A/D conversion rate.
16 V
CC
Positive supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1293
# PIN FUNCTION DESCRIPTION
1 –8 CH0 – CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND.
9 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane.
11 V
Negative Supply Tie V
to most negative potential in the circuit (Ground in single supply applications).
12 AGND Analog Ground AGND should be tied directly to the analog ground plane.
13, 14 REF
, REF
+
Ref. Inputs The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF
+
and REF
.
15 D
IN
Data Input The A/D configuration word is shifted into this input.
16 D
OUT
Digital Data Output The A/D conversion result is shifted out of this output.
17 CS Chip Select Input A logic low on this input enables data transfer.
18 CLK Clock This clock synchronizes the serial data transfer and controls A/D converion rate.
19, 20 AV
CC,
DV
CC
Positive Supplies These supplies must be kept free of noise and ripple by bypassing directly to the analog ground plane. AV
CC
and DV
CC
must be tied together.
LTC1294
# PIN FUNCTION DESCRIPTION
1 –8 CH0 – CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND.
9 COM Common The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane.
11 V
Negative Supply Tie V
to most negative potential in the circuit (Ground in single supply applications).
12 AGND Analog Ground AGND should be tied directly to the analog ground plane.
13, 14 REF
, REF
+
Ref. Inputs The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF
+
and REF
.
15 D
IN
Data Input The A/D configuration word is shifted into this input.
16 D
OUT
Digital Data Output The A/D conversion result is shifted out of this output.
17 CS Chip Select Input A logic low on this input enables data transfer.
18 CLK Clock This clock synchronizes the serial data transfer and controls A/D conversion rate.
19 SSO System Shutdown System Shutdown Output pin will go low when power shutdown is requested.
Output
20 V
CC
Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1296
8
LTC1293/LTC1294/LTC1296
129346fs
W
IDAGRA
B
L
O
C
K
(Pin numbers refer to LTC1294)
Load Circuit for t
dDO
, t
r
and t
f
Load Circuit for t
enSSO
and t
disSSO
D
OUT
1.4V
3k
100pF
TEST POINT
LTC1293 TC02
1.4V
3k
100pF
TEST POINT
LTC1293 TC08
SSO
LT1296
TEST CIRCUITS
On and Off Channel Leakage Current
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1293 TC05
Load Circuit for t
dis
and t
en
INPUT
SHIFT
REGISTER
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
DV
CC
20
ANALOG
INPUT MUX
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
D
OUT
16
CLK
18
CONTROL
AND
TIMING
17
CS
LTC1293 BD
19
15
REF
+
14
DGND
10
V
11
AGND
12
REF
13
COMP
12-BIT
SAR
OUTPUT
SHIFT
REGISTER
D
IN
AV
CC
5V
A
A
I
OFF
I
ON
POLARITY
OFF
CHANNELS
ON CHANNEL
LTC1293 TC1
9
LTC1293/LTC1294/LTC1296
129346fs
TEST CIRCUITS
Voltage Waveforms for t
en
CS
B11
D
OUT
t
en
0.8V
CLK
LTC1293 TC07
START
7
8
4
5
6
3
2
1
D
IN
Voltage Waveform for D
OUT
Rise and Fall Times, t
r,
t
f
D
OUT
0.4V
2.4V
t
r
t
f
LTC1293 TC04
Voltage Waveform for t
dis
Voltage Waveform for D
OUT
Delay Time, t
dDO
CLK
D
OUT
0.8V
t
dDO
0.4V
2.4V
LT
C
12
93
T
C03
Voltage Waveform for for t
enSSO
CLK
0.8V
0.8V
LT
C
12
93
T
C09
SSO
t
en
SSO
Voltage Waveform for t
disSSO
D
OUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1293 TC06
0.8V
2.4V
LTC1293 TC10
SSO
t
dis
SSO
CS

LTC1293CCSW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit Serial I/O ADC w/6 CH MUX
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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