ICS874003BG-05 REVISION B MARCH 21, 2014 11 ©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z
T
) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z
0
) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any transmission-
line reflection issues, the components should be surface mounted
and must be placed as close to the receiver as possible. IDT offers a
full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4A can be used with either
type of output structure. Figure 4B, which can also be used with both
output types, is an optional termination with center tap capacitance
to help filter common mode noise. The capacitor value should be
approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS Termination
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
Z
T
C
Z
O
Z
T
Z
O
Z
T
Z
T
2
Z
T
2
Figure 4A. Standard Termination
Figure 4B. Optional Termination
