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874003BG-05LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
ICS874003BG-05 REVISION B MARCH 21, 2014 4 ©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance,
JA
86.7°C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage V
DD
– 0.16 3.3 V
DD
V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 75 mA
I
DDA
Analog Supply Current 16 mA
I
DDO
Output Supply Current 75 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High
Current
OEA, OEB V
DD
= V
IN
= 3.465V 5 µA
F_SEL0, F_SEL1,
F_SEL2, MR
V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low
Current
OEA, OEB V
DD
= 3.465V, V
IN
= 0V -150 µA
F_SEL0, F_SEL1,
F_SEL2, MR
V
DD
= 3.465V, V
IN
= 0V -5 µA
ICS874003BG-05 REVISION B MARCH 21, 2014 5 ©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR
Table 4C. Differential DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVDS DC Characteristics, V
DD
= V
DDO
= = 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High
Current
CLK V
DD
= V
IN
= 3.465V 150 µA
nCLK V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input Low
Current
CLK V
DD
= 3.465V, V
IN
= 0V -5 µA
nCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Voltage;
NOTE 1
0.15 1.3 V
V
CMR
Common Mode Input
Voltage; NOTE 1, 2
GND + 0.5 V
DD
– 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 275 375 485 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.20 1.35 1.50 V
V
OS
V
OS
Magnitude Change 50 mV
ICS874003BG-05 REVISION B MARCH 21, 2014 6 ©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR
Table 5. AC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods. See IDT Application Note PCI Express Reference Clock Requirements, and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t
REFCLK_HF_RMS
(High
Band) and 3.0 ps RMS for t
REFCLK_LF_RMS
(Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the
PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 98 320 MHz
tjit(cc)
Cycle-to-Cycle Jitter;
NOTE 4
35 ps
tsk(o) Output Skew; NOTE 4, 5 145 ps
tsk(b) Bank Skew; NOTE 4, 6 Bank A 55 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 600 ps
odc Output Duty Cycle 47 53 %
t
j
Phase Jitter Peak-to-Peak;
NOTE 1, 3
100MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.54 ps
125MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
13.13 ps
250MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
12.87 ps
t
REFCLK_HF_RMS
Phase Jitter RMS;
NOTE 2, 3
100MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.22 ps
125MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.17 ps
250MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
1.11 ps
t
REFCLK_LF_RMS
Phase Jitter RMS;
NOTE 2, 3
100MHz output,
Low Band: 10kHz - 1.5MHz
0.25 ps
125MHz output,
Low Band: 10kHz - 1.5MHz
0.22 ps
250MHz output,
Low Band: 10kHz - 1.5MHz
0.22 ps
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

874003BG-05LF

Mfr. #:
Buy 874003BG-05LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PCI EXPRESS JITTER ATTENUATOR
Lifecycle:
New from this manufacturer.
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