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WM8781GEDS/V

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Production Data WM8781
w
PD, January 2012, Rev 4.5
13
MASTER CLOCK AND AUDIO SAMPLE RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock (MCLK). The external master system clock can be applied directly through the MCLK
input pin. In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance of the
ADC.
The master clock is used to operate the digital filters and the noise shaping circuits. The WM8781
supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio sampling
frequency (LRCLK). In Slave Mode, the WM8781 automatically detects the audio sample rate. In
Master Mode, LRCLK is generated for rate 384fs, unless the user changes this to 192fs using the
FSAMPEN pin = z (see Table 7 below). BCLK is also generated in Master Mode, where BCLK=64fs.
Table 6 shows the common MCLK frequencies for different sample rates.
SAMPLING RATE
(LRCLK)
Master Clock Frequency (MHz)
128fs 192fs 256fs 384fs 512fs 768fs
8kHz 1.024 1.536 2.048 3.072 4.096 6.144
16kHz 2.048 3.072 4.096 6.144 8.192 12.288
32kHz 4.096 6.144 8.192 12.288 16.384 24.576
44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688
48kHz 6.144 9.216 12.288 18.432 24.576 36.864
96kHz 12.288 18.432 24.576 36.864 - -
192kHz 24.576 36.864 - - - -
Table 6 Master Clock Frequency Selection
In Slave mode, the WM8781 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available
(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8781 is tolerant of
phase variations or jitter on these clocks.
The WM8781 can operate at sample rates from 8kHz to 192kHz. The WM8781 uses a sigma-delta
modulator that operates at a fixed frequency of 6.144MHz (128 x LRCLK oversampling @ 48kHz
sampling rate). For correct operation of the device and optimal performance, the user must set the
appropriate ADC modulator sampling rate enable. In both Master and Slave Modes, it is
recommended that for 96kHz the user sets FSAMPEN to 1, and for 192kHz set FSAMPEN to z. For
Master Mode 192kHz, FSAMPEN set to z is a requirement.
PIN DESCRIPTION
M/S Master/Slave Selection
0 = Slave Mode (128fs, 192fs,
256fs, 384fs, 512fs, 768fs)
1= Master Mode (384fs, 192fs
when FSAMPEN=z)
FSAMPEN Fast sampling rate enable
0 = 48kHz enable (128x OSR)
1 = 96kHz enable (64x OSR)
z = 192kHz enable (32x OSR)
Table 7 Master/Slave and Sampling Rate Enable Selection
WM8781 Production Data
w
PD, January 2012, Rev 4.5
14
POWER DOWN CONTROL
The WM8781 can be powered down by stopping MCLK. Power down mode using MCLK is entered
after 65536/fs clocks. On power-up, the WM8781 applies the power-on reset sequence described
below.
When MCLK is stopped DOUT is forced to zero.
POWER ON RESET
Figure 10 Power Supply Timing Requirements – power-on
Figure 11 Power Supply Timing Requirements – power-down
Production Data WM8781
w
PD, January 2012, Rev 4.5
15
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = DGND = 0V, T
A
= +25°C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Power Supply Input Timing Information
DVDD level to activate POR –
power on
V
pora
Measured from DGND 0.7 V
AVDD level to activate POR –
power on
V
pora
Measured from AGND 0.7 V
VMID level to activate POR –
power on
V
pora
Measured from AGND 0.7 V
DVDD level to release POR –
power on (see notes 1 and 2)
V
porr
Measured from DGND DVDD Min V
AVDD level to release POR –
power on (see notes 1 and 2)
V
porr
Measured from AGND AVDD Min V
VMID level to release POR –
power on (see notes 1 and 2)
V
porr
Measured from AGND 1 V
POR active period (see notes 1
and 2)
t
por
Measured from POR active to
POR release
30
(note 6)
Defined by DVDD/AVDD/
VMID Rise Time
s
DVDD level to activate POR –
power off (see note 5)
V
por_off
Measured from DGND 0.8 V
AVDD level to activate POR –
power off (see note 5)
V
por_off
Measured from AGND 0.8 V
VMID level to activate POR –
power off (see note 5)
V
por_off
Measured from AGND 0.7 V
Power on - POR propagation
delay through device
t
pon
Measured from rising EDGE of
POR
30 s
Power down - POR propagation
delay through device
t
poff
Measured from falling EDGE of
POR
30 s
Notes:
1. POR is activated when DVDD or AVDD or VMID reach their stated V
pora
level (Figure 10).
2. POR is only released when DVDD and AVDD and VMID have all reached their stated V
porr
levels (Figure 10).
3. The rate of rise of VMID depends on the rate of rise of AVDD, the internal 50kΩ resistance and the external decoupling
capacitor. Typical tolerance of 50K resistor can be taken as +/-20%.
4. If AVDD, DVDD or VMID suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go
below V
por_off,
), then the chip will not reset and will resume normal operation when the voltage is back to the recommended
level again.
5. The chip will enter reset at power down when AVDD or DVDD or VMID falls below V
por_off
. This may be important if the
supply is turned on and off frequently by a power management system.
6. The minimum t
por
period is maintained even if DVDD, AVDD and VMID have zero rise time. This specification is
guaranteed by design rather than test.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

WM8781GEDS/V

Mfr. #:
Buy WM8781GEDS/V
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs STEREO ADC W/384FS MASTER MODE
Lifecycle:
New from this manufacturer.
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