1©2016 Integrated Device Technology, Inc Revision A January 27, 2016
General Description
The 8741004I is a high performance Differential-to-LVDS/0.7V
Differential Jitter Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the PLL
synthesizer and from the system board. The 8741004I has 3 PLL
bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode
will provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 600kHz provides an
intermediate bandwidth that can easily track triangular spread
profiles, while providing good jitter attenuation. The 2MHz bandwidth
provides the best tracking skew and will pass most spread profiles,
but the jitter attenuation will not be as good as the lower bandwidth
modes. Because some 2.5Gb serdes have x20 multipliers while
others have x25 multipliers, the 8741004I can be set for 1:1 mode or
5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
The 8741004I uses IDT’s 3
rd
Generation FemtoClock™
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
PLL Bandwidth
Features
• Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
• One differential clock input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum)
• Full 3.3V operating supply
• Three bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages
Pin Assignment
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
nQB1
QB1
V
DDO
QB0
nQB0
IREF
F_SELB
OEB
GND
GND
nCLK
CLK
8741004I
Data Sheet
Differential-to-LVDS/0.7V Differential
PCI Express™ Jitter Attenuator
