7©2016 Integrated Device Technology, Inc Revision A January 27, 2016
8741004I Data Sheet
Parameter Measurement Information
3.3V HCSL Output Load AC Test Circuit
Differential Input Level
Cycle-to-Cycle Jitter
3.3V LVDS Output Load AC Test Circuit
Bank Skew
LVDS Output Duty Cycle/Pulse Width/Period
Measurement
Point
Measurement
Point
GND
2pF
2pF
0V
IREF
0V
V
DDA
V
DD,
V
DDO
3.3V±5%
3.3V±5%
nCLK
CLK
V
DD
GND
V
OS
Cross Points
V
OD
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
nQA[0:1],
nQB[0:1]
QA[0:1],
QB[0:1]
3.3V ±5%
V
DDA
V
DD,
V
DDO
tsk(b)
nQX0
QX0
nQX1
QX1
Where X is either Bank A or Bank B
nQA[0:1],
nQB[0:1]
QA[0:1],
QB[0:1]
8©2016 Integrated Device Technology, Inc Revision A January 27, 2016
8741004I Data Sheet
Parameter Measurement Information, continued
LVDS Output Rise/Fall Time
Differential Output Voltage Setup
Differential Measurement Points for Duty Cycle/Period
Offset Voltage Setup
Differential Measurement Points for Ringback
HCSL Differential Measurement Points for Rise/Fall
Time
T
STABLE
T
STABLE
V
RB
V
RB
Q - nQ
-150mV
V
RB
= -100mV
V
RB
= +100mV
+150mV
0.0V
SRCC - SRCT
-150mV
+150mV
0.0V
Fall Edge RateRise Edge Rate
9©2016 Integrated Device Technology, Inc Revision A January 27, 2016
8741004I Data Sheet
Parameter Measurement Information, continued
Single-ended Measurement Points for Delta Cross
Point
Differential Measurement Points for Duty Cycle/Period
Differential Measurement Points for Rise/Fall Matching
nQ
Q
V
CROSS
_
MEDIAN
nQ
Q
V
CROSS
_
MEDIAN
V
CROSS
_
MEDIAN
+75mV
V
CROSS
_
MEDIAN
-75mV
t
FALL
t
RISE

8741004BGILF

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 1:4 2-LVDS 2-HCSL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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