OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

8741004BGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
10©2016 Integrated Device Technology, Inc Revision A January 27, 2016
8741004I Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The 8741004I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD,
V
DDA
and V
DDO
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic V
DD
pin and also
shows that V
DDA
requires that an additional 10 resistor along with
a 10F bypass capacitor be connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2. Single-Ended Signal Driving Differential Input
V
DD
V
DDA
3.3V
10
Ω
10µF.01µF
.01µF
V_REF
Single Ended Clock Input
V
DD
CLK
nCLK
R1
1K
C1
0.1u R2
1K
11©2016 Integrated Device Technology, Inc Revision A January 27, 2016
8741004I Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60Ω
2.5V
3.3V
R1
120Ω
R2
120Ω
R3
120
Ω
R4
120
Ω
12©2016 Integrated Device Technology, Inc Revision A January 27, 2016
8741004I Data Sheet
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100 across. If they are left floating, we
recommend that there is no trace attached.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100
differential transmission line environment, LVDS drivers require a
matched load termination of 100 across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
–
+
3.3V
50Ω
50Ω
100Ω Differential Transmission Line
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

8741004BGILF

Mfr. #:
Buy 8741004BGILF
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 1:4 2-LVDS 2-HCSL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet