13©2015 Integrated Device Technology, Inc Revision E December 2, 2015
85304-01 Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number Marking Package Shipping Packaging Temperature
85304AG-01LF ICS85304A01L “Lead-Free” 20 Lead TSSOP Tube 0C to 70C
85304AG-01LFT ICS85304A01L “Lead-Free” 20 Lead TSSOP Tape & Reel 0C to 70C
14©2015 Integrated Device Technology, Inc Revision E December 2, 2015
85304-01 Data Sheet
Revision History Sheet
Rev Table Page Description of Change Date
A
T4B
T4D
T5
4
5
5
V
CMR
values changed from 1.5V min. to 0.5V min.; V
DD
max. to V
CC
- 0.85V max.
V
OH
values changed from 1.9µA min. to V
CC
- 1.4µA min.; 2.3µA max. to V
CC
- 1.0µA.
V
OL
values changed from 1.2µA min. to V
CC
- 2.0µA; 1.6µA max. to V
CC
- 1.7µA max.
Replaced tp
LH
and tp
HL
with t
PD
at the same values.
Replaced t
PW
and values of t
CYCLE
/2 - 40 min., t
CYCLE
/2 typ., t
CYCLE
/2 + 40 max.
with odc at values of 48% min., 50% typ., 52% max.
5/14/01
B
T4D
T5
5 LVPECL DC Characteristics Table - added I
IH
, I
IL
, V
PP
, and V
CMR
rows.
AC Characteristics Table - t
R
and t
F
values changed from 275ps min to 300ps min; 650ps
max. to 700ps max.
5/22/01
C T4D 5 Differential DC Characteristics Table - V
CMR
values changed from V
CC
- 0.85V max. to V
CC.
8/21/01
C 3 Revised Figure 1, CLK_EN Timing Diagram. 10/17/01
C 3 Revised Figure 1, CLK_EN Timing Diagram. 11/2/01
C
T3B 3 Revised Inputs heading from CLK or CLK, nPCLK or nPCLK to CLK or PCLK, nCLK or
nPCLK.
12/28/01
C 8 Added Termination for LVEPCL Output section. 5/30/02
C
6
7
3.3V Output Load Test Circuit Diagram - corrected V
EE
= -1.3V ± 0.135V to
V
EE
= -1.3V ± 0.165V.
Updated Output Rise/Fall Time Diagram.
8/26/02
D
T2
T9
1
2
4
6
8
9
14
Added Lead-Free bullet in Features section.
Pin Characteristics table - changed C
IN
4pF max. to 4pF typical.
Absolute Maximum Ratings, updated Outputs rating.
Updated Parameter Measurement Information.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Ordering Information table - added Lead Free part number.
6/17/04
E
T9
8
9
10
13
Per Document Errata, NEN-08-03, corrected name of PCLK/nPCLK to CLK1/nCLK1
and changed CLK/nCLK to CLK0/nCLK0 throughout the datasheet.
Updated Differential Clock Input Interface section.
Deleted LVPECL Clock Input Interface section.
Added Recommendations for Unused Input and Output Pins section.
Power Considerations - corrected Junction Temperature calculations.
Ordering Information Table - corrected marking.
Updated format throughout the datasheet.
6/20/08
E 3 Corrected Figure 1, CLK_EN Timing Diagram. 7/8/08
E
T4[A:D]
T5
T9
1
4 - 5
5
7
13
Features section - deleted package information
DC Characteristic Tables - corrected table heading temperature from -40C to 85C to
0C to 70C.
AC Characteristic Table - corrected table heading temperature from -40C to 85C to
0C to 70C. Added general note to table.
Updated Wiring the Differential Input to Accept Single-ended Levels application note.
Ordering Information Table - deleted non lead-free parts. Deleted Tape & Reel quantity from
Shipping Packaging column.
12/19/12
E Updated Header and Footer format. 12/2/15
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and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
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85304-01 Data Sheet

85304AG-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1:5 LVPECL Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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