PCA9519 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 10 January 2013 4 of 21
NXP Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
5.2 Pin description
[1] HVQFN24 package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
[2] Port A and port B can be used for either SCL or SDA.
Table 3. Pin description
Symbol Pin Description
TSSOP20 HVQFN24
EN 1 11 enable input (active HIGH)
GND 10 22
[1]
ground (0 V)
V
CC(A)
11 23 port A power supply
A1 19 24 A1 port (low voltage side)
[2]
A2 18 1 A2 port (low voltage side)
[2]
A3 17 2 A3 port (low voltage side)
[2]
A4 16 3 A4 port (low voltage side)
[2]
A5 15 4 A5 port (low voltage side)
[2]
A6 14 5 A6 port (low voltage side)
[2]
A7 13 6 A7 port (low voltage side)
[2]
A8 12 7 A8 port (low voltage side)
[2]
V
CC(B)
20 10 port B power supply
B8 9 12 B8 port (SMBus/I
2
C-bus side)
[2]
B7 8 13 B7 port (SMBus/I
2
C-bus side)
[2]
B6 7 14 B6 port (SMBus/I
2
C-bus side)
[2]
B5 6 15 B5 port (SMBus/I
2
C-bus side)
[2]
B4 5 16 B4 port (SMBus/I
2
C-bus side)
[2]
B3 4 17 B3 port (SMBus/I
2
C-bus side)
[2]
B2 3 18 B2 port (SMBus/I
2
C-bus side)
[2]
B1 2 19 B1 port (SMBus/I
2
C-bus side)
[2]
n.c. - 8, 9, 20, 21
PCA9519 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 10 January 2013 5 of 21
NXP Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9519.
The PCA9519 enables I
2
C-bus or SMBus translation down to V
CC(A)
as low as 1.0 V
without degradation of system performance. The PCA9519 contains 8 bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage and 3.3 V SMBus or 5 V I
2
C-bus. Port B I/Os are over-voltage
tolerant to 5.5 V even when the device is unpowered.
The PCA9519 includes a power-up circuit that keeps the output drivers turned off until
V
CC(B)
is above 2.5 V and the V
CC(A)
is above 0.8 V. V
CC(B)
and V
CC(A)
can be applied in
any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on the
port A (below approximately 0.15 V) turns the corresponding port B driver (either SDA or
SCL) on and drives the port B down to about 0 V. When port A rises above approximately
0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls the
pin HIGH. When the port B falls first and goes below 0.3V
CC(B)
, the port A driver is turned
on and the port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless
the port A voltage goes below V
ILc
. If the port A low voltage goes below V
ILc
, the port B
pull-down driver is enabled until the port A rises above approximately 0.15 V (V
ILc
), then
the port B, if not externally driven LOW, will continue to rise being pulled up by the
external pull-up resistor.
Remark: Ground offset between the PCA9519 ground and the ground of devices on
port A of the PCA9519 must be avoided.
The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of
sinking 3 mA of current at 0.4 V will have an output resistance of 133 or less (R = E / I).
Such a driver will share enough current with the port A output pull-down of the PCA9519
to be seen as a LOW as long as the ground offset is zero. If the ground offset is greater
than 0 V, then the driver resistance must be less. Since V
ILc
can be as low as 90 mV at
cold temperatures and the low end of the current distribution, the maximum ground offset
should not exceed 50 mV.
Bus repeaters that use an output offset are not interoperable with port A of the PCA9519
as their output LOW levels will not be recognized by the PCA9519 as a LOW. If the
PCA9519 is placed in an application where the V
IL
of the port A of the PCA9519 does not
go below its V
ILc
it will pull the port B LOW initially when the port A input transitions LOW
but port B will return HIGH, so it will not reproduce the port A input on port B. Such
applications should be avoided.
Port B is interoperable with all I
2
C-bus slaves, masters, and repeaters and includes the
50 ns glitch filter.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This
can be used to isolate a badly behaved slave on power-up until after the system power-up
reset. It should never change state during an I
2
C-bus operation because disabling during
a bus operation will hang the bus and enabling part way through a bus cycle could
confuse the I
2
C-bus parts being enabled.
PCA9519 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 10 January 2013 6 of 21
NXP Semiconductors
PCA9519
4-channel level translating I
2
C-bus/SMBus repeater
The enable pin should only change state when the bus and the repeater port are in an idle
state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system. Each of the port A I/Os has an
internal pull-up current source and does not require the external pull-up resistor. The
port B is designed to work with Standard mode and Fast mode I
2
C-bus devices in addition
to SMBus devices. Standard mode I
2
C-bus devices only specify 3 mA output drive; this
limits the termination current to 3 mA in a generic I
2
C-bus system where Standard mode
devices and multiple masters are possible. Under certain conditions higher termination
currents can be used.
7. Application design-in information
A typical application is shown in Figure 4. In this example, the CPU is running on a 1.1 V
I
2
C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
When port B of the PCA9519 is pulled LOW by a driver on the I
2
C-bus, a CMOS
hysteresis detects the falling edge when it goes below 0.3V
CC(B)
and causes the internal
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9519 falls, first a comparator detects the falling edge and causes the internal driver
on port B to turn on and pull the port B pin down to ground. In order to illustrate what
would be seen in a typical application, refer to Figure 5
and Figure 6. If the bus master in
Figure 4
were to write to the slave through the PCA9519, waveforms shown in Figure 5
would be observed on the B bus. This looks like a normal I
2
C-bus transmission.
On the port A bus of the PCA9519, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9519. After the 8
th
clock pulse, the data line will
be pulled to the V
OL
of the master device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9519 for a short delay while the port B bus rises above 0.5V
CC(B)
, then it continues
Fig 4. Typical application
002aab642
V
CC(B)
V
CC(A)
PCA9519
A1 B1
A2 B2
EN
10 kΩ
10 kΩ
SDA
SCL
CPU
MASTER
400 kHz
SDA
SCL
bus A bus B
3.3 V
A8 B8
1.1 V
10 kΩ
1.1 V

PCA9519PW,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC REDRIVER I2C 4CH 20TSSOP
Lifecycle:
New from this manufacturer.
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