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9DBV0241AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
DATASHEET
9DBV0241 REVISION F 04/28/16 1 ©2016 Integrated Device Technology, Inc.
2-Output 1.8V PCIe Gen1/2/3 Zero Delay /
Fanout Buffer with Zo=100ohms
9DBV0241
Description
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 2 output enables for clock
management.
Recommended Application
1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
• 2 - 1-200MHz Low-Power (LP) HCSL DIF pairs w/ZO=100Ω
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms (12k-20MHz)
Features/Benefits
• LP-HCSL outputs with Zo=100; saves 8 resistors
compared to standard HCSL outputs
• 35mW typical power consumption in PLL mode; reduced
thermal concerns
• Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device control
• 3.3V tolerant SMBus interface; works with legacy
controllers
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
CONTROL
LOGIC
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SS-
Compatible
PLL
vOE(1:0)#
SCLK_3.3
CLK_IN
C
L
K
_
I
N
#
2
DIF0
DIF1
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS 2 REVISION F 04/28/16
9DBV0241 DATASHEET
Pin Configuration
Power Management Table
Power Connections
Frequency Select Table
PLL Operating Mode
SMBus Address
FB_DNC
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
GND
VDDO1.8
vOE1#
24 23 22 21 20 19
FB_DNC# 1
18
DIF1#
VDDR1.8 2
17
DIF1
CLK_IN 3
16
VDDA1.8
CLK_IN# 4
15
GNDA
GNDR 5
14
DIF0#
GNDDIG 6 13 DIF0
7 8 9 101112
VDDDIG1.8
SCLK_3.3
SDATA_3.3
GND
VDDO1.8
vOE0#
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
9DBV0241
epad is GND
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull
down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
True O/P Comp. O/P
0 X X X Low Low Off
1 Running 0 X Low Low
On
1
1 Running 1 0 Running Running
On
1
1 Running 1 1 Low Low
On
1
CLK_IN OEx# Pin PLL
DIFx
CKPWRGD_PD#
SMBus
OEx bit
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
VDD GND
25
76
11,20 10,21
16 15
Input receiver analo
g
Digital Power
DIF outputs
PLL Analog
Description
Pin Number
FSEL
B
y
te3
[
4:3
]
CLK_IN
(
MHz
)
DIFx
(
MHz
)
00 (Default)
100.00 CLK_IN
01 50.00 CLK_IN
10 125.00 CLK_IN
11 Reserved Reserved
Readback
Control
Address
1101101 x
+ Read/Write bit
REVISION F 04/28/16 3 2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS
9DBV0241 DATASHEET
Pin Descriptions
Pin# Pin Name Type Pin Description
1 FB_DNC# DNC
Complement clock of differential feedback. The feedback output
and feedback input are connected internally on this pin. Do not
connect anything to this pin.
2 VDDR1.8 PWR
1.8V power for differential input clock (receiver). This VDD should
be treated as an Analog power rail and filtered appropriately.
3 CLK_IN IN True Input for differential reference clock.
4 CLK_IN# IN Complementary Input for differential reference clock.
5 GNDR GND Analog Ground pin for the differential input (receiver)
6 GNDDIG GND Ground pin for digital circuitry
7 VDDDIG1.8 PWR 1.8V digital power (dirty power)
8 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
9 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
10 GND GND Ground pin.
11 VDDO1.8 PWR Power supply for outputs, nominally 1.8V.
12 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-
down.
1 =disable outputs, 0 = enable outputs
13 DIF0 OUT Differential true clock output
14 DIF0# OUT Differential Complementary clock output
15 GNDA GND Ground pin for the PLL core.
16 VDDA1.8 PWR 1.8V power for the PLL core.
17 DIF1 OUT Differential true clock output
18 DIF1# OUT Differential Complementary clock output
19 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-
down.
1 =disable outputs, 0 = enable outputs
20 VDDO1.8 PWR Power supply for outputs, nominally 1.8V.
21 GND GND Ground pin.
22 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first
high assertion. Low enters Power Down Mode, subsequent high
assertions exit Power Down Mode. This pin has internal pull-up
resistor.
23 ^vHIBW_BYPM_LOBW#
LATCHED
IN
Trilevel input to select High BW, Bypass or Low BW mode. This
pin is biased to VDD/2 (Bypass mode) with internal pull up/pull down
resistors. See PLL Operating Mode Table for Details.
24 FB_DNC DNC
True clock of differential feedback. The feedback output and
feedback input are connected internally on this pin. Do not connect
anything to this pin.
25 epad GND GND
NOTE:
DNC indicates Do Not Connect anything to this pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9DBV0241AKLF

Mfr. #:
Buy 9DBV0241AKLF
Manufacturer:
IDT
Description:
Clock Buffer PCIe BUFFER, 2 OUT GEN 1/2/3, LOW POWER
Lifecycle:
New from this manufacturer.
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