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9DBV0241AKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS 4 REVISION F 04/28/16
9DBV0241 DATASHEET
Test Loads
Alternate Terminations
The 9DBV family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
Rs
Rs
Low-Power HCSL Differential Output Test Load
2pF 2pF
L
Zo=100ohm
Device
L = 5 inches
REVISION F 04/28/16 5 2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS
9DBV0241 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0241. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
1.8V Supply Voltage VDDxx Applies to all VDD pins -0.5 2.5 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5V V 1, 3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.6V V 1
Storage Temperature Ts -65 150 °C
1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Common Mode
Volta
g
e - DIF_IN
V
COM
Common Mode Input Voltage 150 1000 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFI n
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS 6 REVISION F 04/28/16
9DBV0241 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDx Supply voltage for core and analog 1.7 1.8 1.9 V
Commmercial range 0 25 70 °C
Industrial range -40 25 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
F
ib
yp
Bypass mode 1 200 MHz 2
F
i
p
ll
100MHz PLL mode 60 100.00 140 MHz 2
F
i
p
ll
125MHz PLL mode 75 125.00 175 MHz 2
F
i
p
ll
50MHz PLL mode 30 50.00 65 MHz 2
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,5
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms1,2
Input SS Modulation
Frequency PCIe
f
MODI NPCI e
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30 33 kHz
Input SS Modulation
Frequency non-PCIe
f
MODI N
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
066kHz
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 0.6 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 5 for V
DDSMB
< 3.3V 2.1 3.6 V 4
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
Bus Voltage 1.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 6
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until out
p
uts are >200 mV
5
DIF_IN input
6
The differential in
p
ut clock must be runnin
g
for the SMBus to be active
4
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.8xV
DDSMB
Input Current
Input Frequency
Capacitance
Ambient Operating
Temperature
T
AMB
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

9DBV0241AKLF

Mfr. #:
Buy 9DBV0241AKLF
Manufacturer:
IDT
Description:
Clock Buffer PCIe BUFFER, 2 OUT GEN 1/2/3, LOW POWER
Lifecycle:
New from this manufacturer.
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