2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER WITH ZO=100OHMS 16 REVISION F 04/28/16
9DBV0241 DATASHEET
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Part / Order Number Shipping Packaging Package Temperature
9DBV0241AKLF Tubes 24-pin VFQFPN 0 to +70° C
9DBV0241AKLFT Tape and Reel 24-pin VFQFPN 0 to +70° C
9DBV0241AKILF Tubes 24-pin VFQFPN -40 to +85° C
9DBV0241AKILFT Tape and Reel 24-pin VFQFPN -40 to +85° C
Rev. Initiator Issue Date Description Page #
A RDW 8/13/2012
1. Updated electrical characteristics tables.
2. Move to final.
5-8
B RDW 9/6/2014
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
4. Changed Shipping Packaging from "Trays" to Tubes".
5. Reformatted to new template
Various
C RDW 8/10/2015
1. Updated front page text for family consistency
2. Updated block diagram for family consistency
3. Updated pin configuration to indicate that paddle is ground
4. Added epad as pin 25 to pin descritptions
5. Replaced "Driving LVDS" with "Alternate Terminations", adding
reference to AN-891.
6. Updated "Clock Input Parameters Table" correcting inconsistency with
PCIe SIG specifications.
7. Widened allowable input frequency at each PLL mode frequency.
8. Updated phase jitter parameters with 12k-20M additive phase jitter and
added additive phase jitter graph.
9. Updated NLG24 package drawing with actual package info instead of
eneric drawin
.
1,2,4,5,
6,7,8, 14
D RDW 9/11/2015 1. Corrected block diagram from clock generator to ZDB buffer 1
E RDW 11/4/2015
1. Minor typographical corrections throughout the data sheet
2. Updated test load diagram to generic diagram. Length of test load
listed outside the drawing.
3. Minor updates to electrical tables for formatting. Removed Schmitt
trigger info and output high/low voltage specifications for single-ended
outputs, since this part does not have any.
4. "Low-Power HCSL Outputs" table: corrected inversion of slew rate
setting with specifications. Changed reference from 2 V/ns and 3 V/ns to
slow setting and fast setting. Also change references in SMBus
Bytes[3:2]
5. "Low-Power HCSL Outputs" table: Removed Vswing parameter since
this is an input parameter and is covered in "Clock Input Parameters"
Table.
6. Reduced current consumption limits.
7. Minor updates to other electrical tables.
Various,
4-8,11
F RDW 4/22/2016
1. Updated max frequency of 100MHz PLL mode to 140MHz
2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
6
