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TEA1755T/1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 13 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7.3.1 Multimode operation
The TEA1755T flyback controller can operate in several modes; see Figure 8.
At high output power the converter switches to quasi-resonant mode. The next converter
stroke starts after demagnetization of the transformer and detection of the valley. In
quasi-resonant mode switching losses are minimized. This minimization is achieved by
the converter only switching on when the voltage across the external MOSFET is at its
minimum (see Section 7.3.2
).
Valley switching is active in all operating modes.
To prevent high frequency operation at lower loads, the quasi-resonant operation switches
to discontinuous mode operation with valley skipping. When the frequency limit is
reached, the quasi-resonant operation changes to DCM with valley skipping. The
frequency limit reduces the MOSFET switch-on losses and conducted EMI.
At medium power levels, the controller enters Frequency Reduction (FR) mode. A Voltage
Controlled Oscillator (VCO) controls the frequency. The minimum frequency in this mode
is reduced to approximately 25 kHz. During frequency reduction mode, the primary peak
current is kept at an adjustable minimal level to maintain a high efficiency. Valley switching
is also active in this mode.
At very low power and standby levels, for which the switching frequency would drop below
25 kHz, the converter enters the burst mode. In burst mode, the switching frequency is
36.5 kHz. The primary peak current is fixed in burst mode.
In frequency reduction mode, the PFC controller switches off as soon as the flyback
switching frequency drops below 53 kHz. The flyback maximum frequency changes
linearly with the control V
FBCTRL
(see Figure 9). Hysteresis is added to ensure a stable
PFC switch-on and switch-off. In no-load operation, the switching frequency is reduced to
(almost) zero.
Fig 8. Multimode operation flyback
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TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 14 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7.3.2 Valley switching (HV pin)
A new cycle starts when the external MOSFET is switched on. V
FBSENSE
and V
FBCTRL
determine the on-time. The MOSFET is then switched off and the secondary stroke starts
(see Figure 10
). After the secondary stroke, the drain voltage shows an oscillation with a
frequency of approximately:
(3)
where L
p
is the primary self-inductance of the flyback transformer and C
d
is the
capacitance on the drain node.
When the secondary stroke ends and the internal oscillator voltage is high again, the
circuit waits for the lowest drain voltage before starting a new primary stroke.
Figure 10
shows the drain voltage, valley signal, secondary stroke signal and the internal
oscillator signal.
Valley switching allows high frequency operation because capacitive switching losses are
reduced (see Equation 4
). High frequency operation makes small and cost-effective
magnetic components possible.
(4)
Fig 9. Flyback frequency control
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=
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TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 15 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter because of its good line regulation.
The FBSENSE pin senses the primary current across an external resistor and compares it
to an internal control voltage. The internal control voltage is proportional to V
FBCTRL
(see
Figure 11
).
The FBSENSE pin outputs a current of 2.1 A. This current runs through the resistors
from the FBSENSE pin to the sense resistor R
SENSE
and creates an offset voltage. The
minimum flyback peak current is adjusted using this offset voltage. Adjusting the minimum
peak current level, changes the frequency reduction slope (see Figure 8
).
(1) Start of a new cycle at lowest drain voltage.
(2) Start of a new cycle in a classical Pulse-Width Modulation (PWM) system without valley detection.
Fig 10. Signals for valley switching
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

TEA1755T/1,518

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Buy TEA1755T/1,518
Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters TEA1755T/SO16//1/REEL 13 Q1 DP
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