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TEA1755T/1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 19 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7.3.8 Maximum on-time
The flyback controller limits the on-time of the external MOSFET to 38.5 s. When the
on-time is longer than 38.5 s, the IC stops switching and enters the safe restart state.
7.3.9 Overvoltage protection (FBAUX pin)
An output OVP is implemented in the GreenChip series. In the TEA1755T, the auxiliary
voltage is sensed using the current flowing into the FBAUX pin during the secondary
stroke. The auxiliary winding voltage is a well-defined replica of the output voltage. An
internal filter averages voltage spikes.
An internal up-down counter prevents false OVP detection which can occur during ESD or
lightning events. The internal counter counts up by one when the output voltage exceeds
the OVP trip level within one switching cycle. The internal counter counts down by two
when the output voltage has not exceeded the OVP trip level in one switching cycle.
When the counter has reached six, the IC assumes a true overvoltage, sets the latched
protection and switches off both converters.
The converter only restarts after the OVP latch is reset. In a typical application, the
internal latch is reset when the VINSENSE voltage drops below 750 mV and is then raised
to 860 mV. The latched protection is also reset by removing both the V
CC
and V
HV
.
The demagnetization resistor, R
FBAUX
sets the output voltage V
o(OVP)
at which the OVP
function trips:
(7)
where N
s
is the number of secondary winding and N
aux
is the number of auxiliary winding
of the transformer. Current I
ovp(FBAUX)
is internally trimmed.
Accurate OVP detection is made possible by adjusting the value of R
FBAUX
to the turns
ratio of the transformer.
Fig 15. Flyback soft-start
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V
oOVP
N
s
N
aux
-----------
I
ovp FBAUX
R
FBAUX
V
clamp FBAUX
+=
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 20 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7.3.10 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using
the external sense resistor R
sense2
. The OCP circuit limits V
FBSENSE
to a level set by
V
FBCTRL
(see also Section 7.3.3). The OCP detection is suppressed during the
leading-edge blanking period, t
leb
(equals t
on(fb)min
t
d(FBDRIVER)
), to prevent false
triggering due to switch-on spikes.
7.3.11 Overpower protection
During the flyback converter primary stroke, the flyback converter input voltage is
measured by sensing the current that is drawn from the FBAUX pin.
The current information is used to limit the maximum flyback converter peak current and is
measured using the FBSENSE pin. The internal compensation is such, that a maximum
output power is obtained which is almost independent of the input voltage.
The OPP curve is given in Figure 17
.
7.3.12 Driver (FBDRIVER pin)
The driver circuit for the external power MOSFET gate has a current sourcing capability of
500 mA at 2 V on the FBDRIVER pin and a current sink capability of 1.2 A at 10 V on the
FBDRIVER pin. These capabilities ensure fast switch-on and switch-off of the power
MOSFET for efficient operation.
Fig 16. OCP leading-edge blanking
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Fig 17. Overpower protection curve
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TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 21 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
8. Limiting values
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Voltages
V
CC
supply voltage 0.4 +38 V
V
LATCH
voltage on pin LATCH current limited 0.4 +10 V
V
FBCTRL
voltage on pin FBCTRL 0.4 +9 V
V
PFCCOMP
voltage on pin PFCCOMP 0.4 +5 V
V
VINSENSE
voltage on pin VINSENSE current limited 0.4 +10 V
V
VOSENSE
voltage on pin VOSENSE current limited 0.4 +10 V
V
PFCAUX
voltage on pin PFCAUX 25 +25 V
V
FBSENSE
voltage on pin FBSENSE current limited 0.4 +5 V
V
PFCSENSE
voltage on pin PFCSENSE current limited 0.4 +5 V
V
PFCTIMER
voltage on pin PFCTIMER current limited 0.4 +10 V
V
HV
voltage on pin HV 0.4 +650 V
Currents
I
FBCTRL
current on pin FBCTRL 30 mA
I
FBAUX
current on pin FBAUX 1+1mA
I
PFCSENSE
current on pin PFCSENSE 1+10mA
I
FBSENSE
current on pin FBSENSE 1+10mA
I
FBDRIVER
current on pin FBDRIVER <10% 0.8 +2 A
I
PFCDRIVER
current on pin PFCDRIVER <10% 0.8 +2 A
I
HV
current on pin HV during start-up
and restart
-8mA
= 3 % due to
dV/dt on HV pin
15 +30 mA
General
P
tot
total power dissipation T
amb
<75C-0.6W
T
stg
storage temperature 55 +150 C
T
j
junction temperature 40 +155 C
ESD
V
ESD
electrostatic discharge
voltage
human body
model
pins 1 to 14
[1]
2+2kV
pin 16 (HV)
[1]
2+2kV
charged device
model
500 +500 V
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TEA1755T/1,518

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Buy TEA1755T/1,518
Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters TEA1755T/SO16//1/REEL 13 Q1 DP
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