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TEA1755T/1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 4 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. TEA1755T pin configuration (SOT109-1)
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Table 2. Pin description
Symbol Pin Description
V
CC
1 supply voltage
GND 2 ground
FBCTRL 3 flyback control input
FBAUX 4 auxiliary winding input for demagnetization timing and flyback OVP
LATCH 5 general-purpose protection input
PFCCOMP 6 PFC frequency compensation
VINSENSE 7 mains voltage sense input
PFCAUX 8 auxiliary winding input for demagnetization timing of the PFC
VOSENSE 9 sense input for PFC output voltage
FBSENSE 10 flyback current sense input
PFCSENSE 11 PFC current sense input
PFCDRIVER 12 PFC gate-driver output
FBDRIVER 13 flyback gate-driver output
PFCTIMER 14 PFC override and switch off delay timer
HVS 15 high-voltage safety spacer; not connected
HV 16 high-voltage start-up and flyback valley sensing
TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 5 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
7. Functional description
7.1 General control
The TEA1755T contains a power factor correction circuit controller and a flyback circuit
controller. A typical configuration is shown in Figure 3
.
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially, the capacitor on the V
CC
pin is charged from the high-voltage mains using the HV
pin.
When V
CC
is less than V
trip
, the charge current is I
ch(low)
. This low current protects the IC if
the V
CC
pin is shorted to ground. To ensure a short start-up time, the charge current above
the V
trip
level is increased to I
ch(high)
, until V
CC
reaches V
th(UVLO)
. When V
CC
is between
V
th(UVLO)
and V
startup
, the charge current goes low again to ensure a low safe restart duty
cycle during fault conditions.
The control logic activates the internal circuitry and switches off the HV charge current
when V
CC
passes the V
startup
level. First, the LATCH pin current source is activated and
the soft-start capacitors on the PFCSENSE and FBSENSE pins are charged. Also the
clamp circuit on the PFCCOMP pin is activated.
The PFC circuit is activated when the following conditions are met:
(1) The HV pin can either be connected to the center tap of the flyback transformer or to the drain of MOSFET S2.
Fig 3. A typical TEA1755T configuration
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TEA1755T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1.1 — 13 March 2015 6 of 35
NXP Semiconductors
TEA1755T
HV start-up DCM/QR flyback controller with integrated DCM/QR PFC
controller
• the LATCH pin voltage exceeds the V
en(LATCH)
voltage
• the PFCCOMP pin charging current drops below the absolute value of the
I
en(PFCCOMP)
current
• the soft-start capacitor on the PFCSENSE pin is charged
The flyback converter is also activated if the soft-start capacitor on the FBSENSE pin is
charged. The flyback converter output voltage is then regulated to its nominal output
voltage. The auxiliary winding of the flyback converter takes over the IC supply. See
Figure 4
.
If during start-up, the LATCH pin does not reach the V
en(LATCH)
level before V
CC
reaches
V
th(UVLO)
, the LATCH pin output is deactivated. The charge current is switched on again.
When the flyback converter is started, V
FBCTRL
is monitored. If the output voltage does not
reach its intended regulation level within a specified time, V
FBCTRL
reaches the V
to(FBCTRL)
level. An error is then assumed and a safe restart is initiated.
When one of the safe restart or latched protection functions are triggered, both converters
stop switching and the V
CC
voltage drops to V
th(UVLO)
. A latched protection recharges
capacitor C
VCC
using the HV pin, but does not restart the converters. To provide safe
restart protection, the capacitor is recharged using the HV pin and the device restarts (see
block diagram, Figure 1
).
If OVP is triggered on the PFC circuit (V
VOSENSE
>V
OVP(VOSENSE)
), the PFC controller
stops switching until the V
VOSENSE
< V
OVP(VOSENSE)
. If a mains UVP is detected,
V
VINSENSE
<V
stop(VINSENSE)
, the PFC controller stops switching until
V
VINSENSE
>V
start(VINSENSE)
again.
When the V
CC
pin voltage drops under the UVLO level, both controllers stop switching and
enter safe restart mode. In the safe restart mode, the V
CC
pin capacitor is recharged using
the HV pin.
At very low burst mode repetition rates, V
CC
can drop under the UVLO level. The UVLO
protection feature V
prot(UVLO)
prevents the decrease when the IC is in burst mode.
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TEA1755T/1,518

Mfr. #:
Buy TEA1755T/1,518
Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters TEA1755T/SO16//1/REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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