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FM28V100-TG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
FM28V100
1-Mbit (128 K × 8) F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-86202 Rev. *E Revised August 12, 2015
1-Mbit (128 K × 8) F-RAM Memory
Features
■ 1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128 K × 8
❐ High-endurance 100 trillion (10
14
) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Page mode operation to 30 ns cycle time
❐ Advanced high-reliability ferroelectric process
■ SRAM compatible
❐ Industry-standard 128 K × 8 SRAM pinout
❐ 60-ns access time, 90-ns cycle time
■ Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
■ Low power consumption
❐ Active current 7 mA (typ)
❐ Standby current 90 A (typ)
■ Low-voltage operation: V
DD
= 2.0 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ 32-pin thin small outline package (TSOP) Type I
■ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM28V100 is a 128 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V100 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by chip enable or simply by changing the address. The
F-RAM memory is nonvolatile due to its unique ferroelectric
memory process. These features make the FM28V100 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The device is available in a 32-pin TSOP I surface mount
package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Logic Block Diagram
Address Latch
CE
Control
Logic
WE
Row Decoder
A
I/O Latch & Bus DriverOE
DQ
128 K x 8
F-RAM Array
. . .
Column Decoder
. . .
16-3
A
2-0
7-0
A
16-0
1
, CE
2
FM28V100
Document Number: 001-86202 Rev. *E Page 2 of 18
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Device Operation ..............................................................4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ...........................................................4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
SRAM Drop-In Replacement ....................................... 5
Maximum Ratings .............................................................6
Operating Range ...............................................................6
DC Electrical Characteristics ..........................................6
Data Retention and Endurance .......................................7
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Conditions ..........................................................7
AC Switching Characteristics .........................................8
SRAM Read Cycle ...................................................... 8
SRAM Write Cycle ....................................................... 9
Power Cycle Timing .......................................................12
Functional Truth Table ...................................................13
Ordering Information ......................................................14
Ordering Code Definitions ......................................... 14
Package Diagrams ..........................................................15
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure ....................................................... 16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
FM28V100
Document Number: 001-86202 Rev. *E Page 3 of 18
Pinout
Figure 1. 32-pin TSOP I pinout
Pin Definitions
Pin Name I/O Type Description
A
16
–A
0
Input Address inputs: The 17 address lines select one of 131,072 bytes in the F-RAM array. The lowest two
address lines A
2
–A
0
may be used for page mode read and write operations.
DQ
7
–DQ
0
Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V100 to write
the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for
page mode write cycles.
CE
1
, CE
2
Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE
1
(while
CE
2
is HIGH) or the rising edge of CE
2
(while CE
1
is LOW). The entire address is latched internally at
this point. The CE
2
pin is pulled up internally. Subsequent changes to the A
2
–A
0
address inputs allow
page mode operation.
OE
Input Output Enable: When OE is LOW, the FM28V100 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
V
SS
Ground Ground for the device. Must be connected to the ground of the system.
V
DD
Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
A
0
DQ
0
DQ
1
DQ
2
DQ
7
A
10
DQ
6
DQ
3
DQ
5
A
1
WE
V
DD
A
16
A
14
A
12
A
7
A
6
A
5
A
11
A
9
A
8
A
13
32-pin TSOP I
(x 8)
Top view
(not to scale)
1
2
3
4
13
14
5
6
7
8
9
10
11
12
20
19
23
22
21
25
24
28
27
26
30
29
32
31
15
16
18
17
A
4
NC
A
2
V
SS
DQ
4
CE
2
A
15
A
3
CE
1
OE
[1]
Note
1. Reserved for address A
17
on 2-Mbit device.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

FM28V100-TG

Mfr. #:
Buy FM28V100-TG
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 1M (128Kx8) 2.2-3.6V F-RAM
Lifecycle:
New from this manufacturer.
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