FM28V100
Document Number: 001-86202 Rev. *E Page 10 of 18
Figure 4. Read Cycle Timing 1 (CE
1
LOW, CE
2
HIGH, OE LOW)
Figure 5. Read Cycle Timing 2 (Chip Enable Controlled)
Figure 6. Page Mode Read Cycle Timing
[10]
Valid Data
A
DQ
t
RC
Previous Data
t
OH
t
AA
t
OH
16-0
7-0
D out
CE
A
OE
t
AS
t
CE
t
CA
t
PC
t
OE
t
OHZ
t
HZ
t
AH
CE
1
2
16-0
DQ
7-0
t
HZ
OE
t
AS
t
CA
t
OE
t
CE
t
OHZ
t
AAP
t
OHP
t
PC
Col 0
Data 0
Col 1
Data 1
Col 2
Data 2
CE
1
CE
2
A
16-3
A
2-0
DQ
7-0
Note
10. Although sequential column addressing is shown, it is not required
FM28V100
Document Number: 001-86202 Rev. *E Page 11 of 18
Figure 7. Write Cycle Timing 1 (WE
Controlled)
[11]
Figure 8. Write Cycle Timing 2 (CE Controlled)
Figure 9. Write Cycle Timing 3 (CE
1
LOW, CE
2
HIGH)
[11]
t
DS
t
DH
t
WZ
D in
WE
t
CA
t
PC
t
WP
t
CW
t
AS
D out
D out
t
WX
t
HZ
t
WLC
CE
1
CE
2
A
16-0
DQ
7-0
t
DS
t
DH
D in
t
CA
t
PC
t
WS
t
AS
t
WH
t
DS
t
AH
WE
CE
1
CE
2
A
16-0
DQ
7-0
t
DH
t
WZ
t
WX
D in
A
WE
DQ
t
WC
t
WLA
t
DS
t
AWH
D out D out D in
16-0
7-0
Note
11. OE
(not shown) is LOW only to show the effect of WE on DQ pins.
FM28V100
Document Number: 001-86202 Rev. *E Page 12 of 18
Figure 10. Page Mode Write Cycle Timing
t
ASP
WE
t
CA
t
PC
t
CW
Col 0 Col 1
Data 0
Col 2
t
AS
Data 1
t
WP
t
DH
Data 2
OE
t
AHP
t
PWC
t
AH
t
WLC
CE
1
CE
2
A
16-3
DQ
7-0
A
2-0
t
DS
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
t
PU
Power-up (after V
DD
min. is reached) to first access time 250 µs
t
PD
Last write (WE HIGH) to power down time 0 µs
t
VR
[12]
V
DD
power-up ramp rate 50 µs/V
t
VF
[12]
V
DD
power-down ramp rate 100 µs/V
Figure 11. Power Cycle Timing
V
DD
t
VF
V
DD
min
min
V
DD
t
VR
t
PU
t
PD
Access Allowed
Note
12. Slope measured at any point on the V
DD
waveform.

FM28V100-TG

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 1M (128Kx8) 2.2-3.6V F-RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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