Document Number: 001-86202 Rev. *E Page 9 of 18
SRAM Write Cycle
t
WC
t
WC
Write cycle time 105 – 90 – ns
t
CA
– Chip enable active time 70 – 60 – ns
t
CW
t
SCE
Chip enable to write enable HIGH 70 – 60 – ns
t
PC
– Pre-charge time 35 – 30 – ns
t
PWC
– Page mode write enable cycle time 40 – 30 – ns
t
WP
t
PWE
Write enable pulse width 22 – 18 – ns
t
AS
t
SA
Address setup time (to CE
1
, CE
2
active)0–0–ns
t
AH
t
HA
Address hold time (Chip Enable Controlled) 70 – 60 – ns
t
ASP
– Page mode address setup time (to WE LOW)8–5–ns
t
AHP
– Page mode address hold time (to WE LOW) 20 – 15 – ns
t
WLC
t
PWE
Write enable LOW to chip disabled 30 – 25 – ns
t
WLA
– Write enable LOW to A
16-3
change 30 – 25 – ns
t
AWH
– A
16-3
change to write enable HIGH 105 – 90 – ns
t
DS
t
SD
Data input setup time 20 – 15 – ns
t
DH
t
HD
Data input hold time 0–0–ns
t
WZ
[7, 8]
t
HZWE
Write enable LOW to output HI-Z – 10 – 10 ns
t
WX
[8]
– Write enable HIGH to output driven 5 – 5 – ns
t
WS
[8, 9]
– Write enable to CE LOW setup time 0 – 0 – ns
t
WH
[8, 9]
– Write enable to CE HIGH hold time 0 – 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters
[4]
Description
V
DD
=
2.0 V to 2.7 V V
DD
=
2.7 V to 3.6 V
Unit
Cypress
Parameter
Alt Parameter Min Max Min Max
Notes
7. t
WZ
is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
8. This parameter is characterized but not 100% tested.
9. The relationship between CE
(falling edge of CE
1
(while CE
2
is HIGH), or the rising edge of CE
2
(while CE
1
is LOW) and WE determines if a chip enable or WE
controlled write occurs.
