LTC2954
13
2954fb
Figure 7. PowerPath Control with 6V Undervoltage Detect
width detected is 30μs. If there are glitches on the resis-
tor pull-up voltage that are wider than 30μs and transition
below 0.6V, then an appropriate bypass capacitor should
be connected to the KILL pin. The optional C
PDT
external
capacitor extends the length of time (beyond 64ms) that
the PB input must be held low before releasing the enable
output.
High Voltage PowerPath Switching
The high voltage EN open drain output of the LTC2954-2
is designed to switch on/off an external power PFET. This
allows a user to connect/disconnect a power supply (or
battery) to its load by toggling the PB pin. Figure 7 shows
the LTC2954-2 controlling a two cell Li-Ion battery ap-
plication. The KILL pin is connected to the output of the
TYPICAL APPLICATIONS
V
OUT
R1
909k
1%
R4
100k
1%
C3*
0.1μF
2954 F07
C4
0.1μF
CERAMIC
*OPTIONAL
V
TH
= 0.6V INPUT
R5
100k
R9
100k
M1
+
4.2V
SINGLE CELL
Li-Ion BATTERY
+
4.2V
SINGLE CELL
Li-Ion BATTERY
OPTIONAL GLITCH
FILTER CAPACITOR
V
OUT
,TRIP POINT = 6V
PB
EN
INT
KILL
LTC2954-2
GND ONT PDT
V
IN
C
ONT
*
0.033μF
PFET through a resistive divider. The KILL pin serves as
a voltage monitor. When V
OUT
drops below 6V, causing a
KILL voltage below V
KILL(TH)
, the EN pin becomes an open
circuit 30μs later. Since the PDT pin is open-circuited, the
power-down debounce time defaults to 64ms.
PB Pin in a Noisy Environment
The rugged PB pin is designed to operate in noisy environ-
ments. Transients below ground (>6V) and above V
IN
(<33V) will not damage the rugged PB pin. Additionally,
the PB pin can withstand ESD HBM strikes up to ±10kV.
In order to keep external noise from coupling inside the
LTC2954, place an R-C network close to the PB pin. A 5.1k
resistor and a 0.1μF capacitor should suffice for most noisy
applications (see Figure 8).
Figure 8. Noisy PB Trace
PB
V
IN
LTC2954-1
GND ONT
R6
5.1k
2954 F08
TRACE
CAPACITANCE
PARASITICS
C5
0.1μF
DETAILS OMITTED
FOR CLARITY
TRACE
INDUCTANCE
NOISE
EN
INT
KILL
PDT
V
IN
LTC2954
14
2954fb
External Pull-Up Resistor On PB
An internal pull-up resistor on the PB pin makes an ex-
ternal pull-up resistor unnecessary. Leakage current on
the PB board trace, however, will affect the open circuit
voltage on the PB pin. If the leakage is too large (>2μA),
the PB voltage may fall close to the threshold window. To
mitigate the effect of the board leakage, a 10k resistor to
V
IN
is recommended (see Figure 9).
Figure 9. External Pull-Up Resistor On PB Pin
Reverse Battery Protection
To protect the LTC2954 from a reverse battery connec-
tion, place a 1k resistor in series with the V
IN
pin (see
Figure 10).
TYPICAL APPLICATIONS
PB
V
IN
LTC2954-1/
LTC2954-2
GND
EXTERNAL BOARD
LEAKAGE CURRENT
100k
2.4V
R7
10k
2954 F09
>2μA
PINS OMITTED
FOR CLARITY
IF EXTERNAL PARASITIC BOARD
LEAKAGE >2μA, USE EXTERNAL
PULL-UP RESISTOR
V
IN
LTC2954
15
2954fb
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702 Rev B)
PACKAGE DESCRIPTION
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.15 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
14
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB8) DFN 0905 REV B
0.25 ± 0.05
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
PIN 1
R = 0.20 OR
0.25 × 45°
CHAMFER
0.50 BSC

LTC2954CTS8-1#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Push Button On/Off Controller with U Interrupt for Menu Driven Applications
Lifecycle:
New from this manufacturer.
Delivery:
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