8302AMI-01LF

8302I-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 7, 20164
TABLE 4B. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
TABLE 4A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low-to-High; NOTE 1 1.8 2.7 ns
tsk(o) Output Skew; NOTE 2, 4 165 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 800 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 300 800 ps
odc Output Duty Cycle
ƒ 133MHz
45 55 %
133MHz < ƒ 250MHz
40 60 %
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 250 MHz
tp
LH
Propagation Delay, Low-to-High; NOTE 1 1.9 2.9 ns
tsk(o) Output Skew; NOTE 2, 4 250 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 900 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 850 ps
odc Output Duty Cycle
ƒ 133MHz
45 55 %
133MHz < ƒ 250MHz
40 60 %
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
8302I-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 7, 20165
PARAMETER MEASUREMENT INFORMATION
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8302I-01 Data Sheet
©2016 Integrated Device Technology, Inc Revision A March 7, 20166
TRANSISTOR COUNT
The transistor count for 8302I-01 is: 322
TABLE 5. θ
JA
VS. AIR FLOW TABLE FOR 8 LEAD SOIC
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
RELIABILITY INFORMATION

8302AMI-01LF

Mfr. #:
Manufacturer:
Description:
Clock Buffer 2 LVCMOS OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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