74LVC_LVCH2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 February 2013 12 of 29
NXP Semiconductors
74LVC2T45-Q100; 74LVCH2T45-Q100
Dual supply translating transceiver; 3-state
[1] t
PZH
and t
PZL
are calculated values using the formula shown in Section 14.4 “Enable times.
t
PLZ
LOW to OFF-state
propagation delay
DIR to A 1.4 3.7 1.4 3.7 1.3 3.7 1.0 3.7 0.9 3.7 ns
DIR to B 2.3 13.1 2.4 12.1 1.9 7.4 2.3 7.0 1.8 4.5 ns
t
PZH
OFF-statetoHIGH
propagation delay
DIR to A
[1]
- 23.6 - 18.9 - 12.2 - 11.4 - 8.4 ns
DIR to B
[1]
- 20.3 - 18.8 - 11.2 - 9.1 - 7.6 ns
t
PZL
OFF-state to LOW
propagation delay
DIR to A
[1]
- 28.1 - 23.1 - 14.3 - 12.0 - 9.2 ns
DIR to B
[1]
- 20.7 - 17.6 - 11.6 - 9.9 - 8.9 ns
Table 12. Dynamic characteristics for temperature range 40 C to +85 C
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5.
Symbol Parameter Conditions V
CC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
Table 13. Dynamic characteristics for temperature range 40 C to +125 C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6
; for wave forms see Figure 4 and Figure 5.
Symbol Parameter Conditions V
CC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
V
CC(A)
= 1.4 V to 1.6 V
t
PLH
LOW to HIGH
propagation delay
A to B 2.5 23.5 2.1 19.4 1.8 14.9 1.5 13.0 1.4 11.6 ns
B to A 2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns
t
PHL
HIGH to LOW
propagation delay
A to B 2.3 21.3 1.9 16.9 1.6 13.0 1.5 12.0 1.5 11.9 ns
B to A 2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns
t
PHZ
HIGH to OFF-state
propagation delay
DIR to A 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 ns
DIR to B 3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 ns
t
PLZ
LOW to OFF-state
propagation delay
DIR to A 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 ns
DIR to B 2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns
t
PZH
OFF-statetoHIGH
propagation delay
DIR to A
[1]
- 43.7 - 40.1 - 26.8 - 24.9 - 23.6 ns
DIR to B
[1]
- 36.1 - 32.0 - 27.5 - 25.6 - 24.2 ns
t
PZL
OFF-state to LOW
propagation delay
DIR to A
[1]
- 48.6 - 45.1 - 26.7 - 25.0 - 23.5 ns
DIR to B
[1]
- 41.9 - 37.5 - 33.6 - 32.6 - 32.5 ns
V
CC(A)
= 1.65 V to 1.95 V
t
PLH
LOW to HIGH
propagation delay
A to B 2.3 21.1 1.9 19.5 1.9 10.3 1.5 8.0 1.2 7.5 ns
B to A 2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns
t
PHL
HIGH to LOW
propagation delay
A to B 2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 ns
B to A 1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns
t
PHZ
HIGH to OFF-state
propagation delay
DIR to A 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 ns
DIR to B 2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2 9.1 ns
t
PLZ
LOW to OFF-state
propagation delay
DIR to A 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 ns
DIR to B 2.2 19.4 2.3 17.6 1.9 10.2 2.4 9.3 2.1 7.9 ns
t
PZH
OFF-statetoHIGH
propagation delay
DIR to A
[1]
- 38.8 - 37.1 - 27.8 - 26.4 - 24.6 ns
DIR to B
[1]
- 32.7 - 31.1 - 21.9 - 19.6 - 19.1 ns
74LVC_LVCH2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 February 2013 13 of 29
NXP Semiconductors
74LVC2T45-Q100; 74LVCH2T45-Q100
Dual supply translating transceiver; 3-state
t
PZL
OFF-state to LOW
propagation delay
DIR to A
[1]
- 43.5 - 39.9 - 26.9 - 25.3 - 22.6 ns
DIR to B
[1]
- 38.0 - 34.7 - 28.3 - 26.8 - 26.6 ns
V
CC(A)
= 2.3 V to 2.7 V
t
PLH
LOW to HIGH
propagation delay
A to B 2.0 19.7 2.0 17.6 1.3 9.4 1.1 6.9 0.9 5.3 ns
B to A 1.8 14.9 1.9 10.3 1.3 9.4 1.2 8.8 0.9 8.3 ns
t
PHL
HIGH to LOW
propagation delay
A to B 2.0 17.4 1.8 14.2 1.2 8.3 1.1 6.0 0.8 5.1 ns
B to A 1.6 13.0 1.7 9.4 1.2 8.3 1.1 7.7 0.8 6.9 ns
t
PHZ
HIGH to OFF-state
propagation delay
DIR to A 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 ns
DIR to B 2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0 7.6 ns
t
PLZ
LOW to OFF-state
propagation delay
DIR to A 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 ns
DIR to B 2.0 16.1 2.2 14.6 1.8 9.9 2.2 9.3 1.6 6.4 ns
t
PZH
OFF-statetoHIGH
propagation delay
DIR to A
[1]
- 31.0 - 24.9 - 19.3 - 18.1 - 14.7 ns
DIR to B
[1]
- 26.1 - 24.0 - 15.8 - 13.3 - 11.7 ns
t
PZL
OFF-state to LOW
propagation delay
DIR to A
[1]
- 37.8 - 33.0 - 20.4 - 18.0 - 14.5 ns
DIR to B
[1]
- 26.4 - 23.2 - 17.3 - 15.0 - 14.1 ns
V
CC(A)
= 3.0V to 3.6V
t
PLH
LOW to HIGH
propagation delay
A to B 2.0 18.9 1.8 17.1 1.2 8.8 0.7 6.2 0.6 4.9 ns
B to A 1.5 13.0 1.5 8.0 1.1 6.9 0.6 6.2 0.5 6.0 ns
t
PHL
HIGH to LOW
propagation delay
A to B 1.9 17.2 1.8 13.9 1.1 7.7 0.7 5.5 0.6 4.4 ns
B to A 1.5 12.0 1.6 7.9 1.1 6.0 0.7 5.5 0.6 5.0 ns
t
PHZ
HIGH to OFF-state
propagation delay
DIR to A 2.0 8.1 2.0 8.1 2.0 8.1 2.0 8.1 2.4 8.1 ns
DIR to B 2.6 19.8 2.6 18.2 2.0 11.2 2.4 9.5 1.9 7.0 ns
t
PLZ
LOW to OFF-state
propagation delay
DIR to A 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 ns
DIR to B 2.0 15.0 2.1 13.8 1.7 8.6 2.0 7.9 1.5 5.4 ns
t
PZH
OFF-statetoHIGH
propagation delay
DIR to A
[1]
- 28.0 - 21.8 - 15.5 - 14.1 - 11.4 ns
DIR to B
[1]
- 25.1 - 23.3 - 15.0 - 12.4 - 11.1 ns
t
PZL
OFF-state to LOW
propagation delay
DIR to A
[1]
- 31.8 - 26.1 - 17.2 - 15.0 - 12.0 ns
DIR to B
[1]
- 25.3 - 22.0 - 15.8 - 13.6 - 12.5 ns
V
CC(A)
= 4.5V to 5.5V
t
PLH
LOW to HIGH
propagation delay
A to B 1.9 18.3 1.7 16.7 0.9 8.3 0.6 6.0 0.4 4.3 ns
B to A 1.4 11.6 1.2 7.5 0.9 5.3 0.6 4.9 0.4 4.3 ns
t
PHL
HIGH to LOW
propagation delay
A to B 2.0 16.9 1.6 13.5 0.9 6.9 0.6 5.0 0.4 3.9 ns
B to A 1.5 11.9 1.5 7.7 0.8 5.1 0.6 4.4 0.4 3.9 ns
t
PHZ
HIGH to OFF-state
propagation delay
DIR to A 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 ns
DIR to B 2.6 19.1 2.6 17.8 2.0 10.7 2.4 8.8 2.2 6.3 ns
t
PLZ
LOW to OFF-state
propagation delay
DIR to A 1.2 4.1 1.2 4.1 1.1 4.1 0.9 4.1 0.8 4.1 ns
DIR to B 2.0 14.5 2.1 13.4 1.7 8.2 2.0 7.7 1.6 5.0 ns
Table 13. Dynamic characteristics for temperature range 40 C to +125 C
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5.
Symbol Parameter Conditions V
CC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
74LVC_LVCH2T45_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 22 February 2013 14 of 29
NXP Semiconductors
74LVC2T45-Q100; 74LVCH2T45-Q100
Dual supply translating transceiver; 3-state
[1] t
PZH
and t
PZL
are calculated values using the formula shown in Section 14.4 “Enable times.
12. Waveforms
t
PZH
OFF-statetoHIGH
propagation delay
DIR to A
[1]
- 26.1 - 20.9 - 13.5 - 12.6 - 9.3 ns
DIR to B
[1]
- 22.4 - 20.8 - 12.4 - 10.1 - 8.4 ns
t
PZL
OFF-state to LOW
propagation delay
DIR to A
[1]
- 31.0 - 25.5 - 15.8 - 13.2 - 10.2 ns
DIR to B
[1]
- 22.9 - 19.5 - 12.9 - 11.0 - 9.9 ns
Table 13. Dynamic characteristics for temperature range 40 C to +125 C
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6; for wave forms see Figure 4 and Figure 5.
Symbol Parameter Conditions V
CC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min Max Min Max Min Max Min Max
Measurement points are given in Table 14.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 4. The data input (A, B) to output (B, A) propagation delay times
001aaj644
nA, nB input
nB, nA output
t
PLH
t
PHL
GND
V
I
V
OH
V
M
V
M
V
OL
Measurement points are given in Table 14.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 5. Enable and disable times
001aae968
t
PZL
t
PZH
t
PHZ
t
PLZ
GND
GND
V
I
V
CCO
V
OL
V
OH
V
M
V
M
V
M
V
X
V
Y
outputs
disabled
outputs
enabled
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
DIR input

74LVC2T45DC-Q100H

Mfr. #:
Manufacturer:
Nexperia
Description:
Bus Transceivers 74LVC2T45DC-Q100/VSSOP8/REEL 7
Lifecycle:
New from this manufacturer.
Delivery:
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